The complexity of node rewriting graph grammars is investigated, i.e. the membership problem for sets of graphs L(G) generated by directed, node and edge label controlled graph grammars G. We improve known results on the membership problem and comprise them into the following sharp characterization of the P vs. NP borderline, which is an "if and only if" result.

Computational Aspects of Vlsi

On Polynomial Time Graph Grammars

Decomposing a polygon into simple shapes is a basic problem in computational geometry, with applications in pattern recognition and integrated circuit manufacture. Here we examine the special case of covering a rectilinear polygon (or polyomino) with the minimum number of rectangles, with overlapping allowed. The problem is NP-hard. However, we give here an O(v2) algorithm for constructing a minimum rectangle cover, when the polygon is vertically convex. (Here v is the number of vertices.) The problem is first reduced to a 1-dimensional interval “basis” problem. In showing our algorithm produces an optimal cover we give a new proof of a minimum basis-maximum independent set duality theorem first proved by E. Gyori (J. Combin Theory Ser. B 37, No. 1, 1–9).

An algorithm for covering polygons with rectangles

Embedding mesh of trees in the hypercube

Layout graph grammars are a grammatical or rule-based method for the construction of graphs and of their drawings. As such they are representatives of the so-called declarative approach. A layout graph grammar consists of an underlying context-free graph grammar and of layout specifications. These are attached to the productions and consist of position relations and distances between the vertices of the productions. The layout specifications are often derived from drawings of the productions and can be defined in terms of labelled graphs.

background or methods

/pdf/designing-graph-drawings-by-layout-graph-grammars-3660gu1mn3.pdf

Designing Graph Drawings by Layout Graph Grammars

We study digital clock synchronization for multiprocessor systems, where processors are triggered by a common clock pulse and communicate with others via shared memory.

A self-stabilizing digital clock synchronization protocol for systems with a general communication graph is presented. The protocol can commence in an arbitrary non-consistent system state and converges to a legitimate state in which the clocks are synchronized and incremented by one in every subsequent pulse.

To enhance the fault-tolerance of our protocol, we allow that during and following convergence processors may stop operating. Crash failures may partition the communication graph into several connected components. Our protocol synchronizes the clocks of the processors in every such connected component. For the case in which faulty processors can exhibit Byzantine behavior, we prove that there is no digital clock synchronization protocol that tolerates even one single faulty processor.

Computational Aspects of Vlsi

Citations

On Polynomial Time Graph Grammars

An algorithm for covering polygons with rectangles

Embedding mesh of trees in the hypercube

Designing Graph Drawings by Layout Graph Grammars

Possible and Impossible Self-Stabilizing Digital ClockSynchronization in General Graphs

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