We provide analytical "back of the envelope" calculations for the choice of optimal supply and threshold voltages and sizing for minimum energy-delay product. Based on such calculations we then show that a circuit design style with separate logic and buffer stages offers a better energy-delay product in the presence of interconnect parasitics.

Computational Aspects of Vlsi

Optimal voltages and sizing for low power [CMOS VLSI]

Multiprocessor computer systems are becoming increasingly important as vehicles for solving computationally expensive problems. Synchronization among the processors is achieved with a variety of clock configurations. A new notion of fault-tolerance for clock synchronization algorithms is defined, tailored to the requirements and failure patterns of shared memory multiprocessors. Algorithms in this class can tolerate any number of napping processors, where a napping processor can fail by repeatedly ceasing operation for an arbitrary time interval and then resume operation without necessarily recognizing that a fault has occurred. These algorithms guarantee that, for some fixed k, once a processor P has been working correctly for at least k time, then as long as P continues to work correctly, (1) P does not adjust its clock, and (2) P's clock agrees with the clock of every other processor that has also been working correctly for at least k time. Because a working processor must synchronize in a fixed amount of time regardless of the actions of the other processors, these algorithms are called wait-free. Another useful type of fault-tolerance is called self-stabilization: starting with an arbitrary state of the system, a self-stabilizing algorithm eventually reaches a point after which it correctly performs its task.

Additional excerpts

Wait-free clock synchronization

An algorithm is presented sorting N=n1n2...nr, r≧2, elements on an n1 × n2 × ... × nr mesh-connected array of processors within 2(n1+...+nr−1)+nr+0(n11−e+...+nr1−e), ɛ>0, data interchange steps. Hence this algorithm asymptotically matches the quite recently given lower bound for r-dimensional meshes. The asymptotically optimal lower bound of (2r/21/r) N1/r interchange steps can only be obtained on r-dimensional meshes withaspect ratio ni : nr=1 : 2 for all i=1,...,r−1. Moreover, for meshes with wraparound connections the slightly altered algorithm only need 1.5(n1+...+nr−1)+nr+0(n11−e+...+nr1−e) data interchange steps, which asymptotically is significantly smaller than the lower bound for sorting on meshes without wrap-arounds.

background

Optimal Sorting on Multi-Dimensionally Mesh-Connected Computers

ion o f a concept that we had of a general physical compute r or \"comput ing environment .\" We pictured a finite set of elements, each a processor or a data variable, each with a limited amount of memory, each implemented as a physical entity which occupies some finite volume which is at least a constant v. Each element has a certain location in 3D space and over lapping of elements is not allowed. Memory elements can be viewed as special processors which, for instance, on reception o f a \"read\" request send their value as reflected by their state in the direction of arrival of the request. Assuming that all processors have the same size and form and are located at discrete ra ther than continuous coordinates does not seem to be essential. A discussion o f similar abstractions for VLSI models can be found at [23]. We suggest that informat ion t ransfer between processors is a fundamenta l issue of parallel computat ion which deserves explicit representa t ion in the abstract model. Elements t ransfer data between them by t ransmit t ing information which travels th rough space no faster than the speed o f light. Messages carr ied by electromagnetic radiat ion general ly can overlap o ther messages in space. However, the inevitable existence o f noise and accuracy limitations lead us to assume that a finite volume o f empty space cannot have more than a bounded number o f distinguishable states. I t is worthwhile to quote Tur ing ([22] section 9) in this respect: I shall also suppose that the number o f symbols which may be pr in ted is finite. I f we were to allow an infinity o f symbols, then there would be symbols differ ing to an arbitrari ly small extent. We will also suppose that the number o f states of mind which need be taken into account is finite. T h e reasons for this are of the same character as those which restrict the number o f symbols. I f we admit ted an infinity of states o f mind, some o f them will be 'arbitrarily close' and will be confused. Minsky ([16] p. 109) elaborates, refer r ing to the last paragraph: I f . . . he has in mind physical states of a brain, then one would indeed expect that for sufficiently similar states there will be a chance o f r andom transitions, e.g., because o f thermal or quantum phenomena . The re is a limit to the amount of informat ion that can be recovered from any physical system of limited size. 6 6 October 1992/Vo1.35, No.10/COMMUNICATIONSOFTHE ACM In other words, a finite volume of space cannot store, even temporarily, more than a bounded number of bits of information. This observation amounts to setting a lower bound on the volume \"occupied\" by a flying message bit, a l though generally, in reality, no region of space is the exclusive realm of any single bit. The result of our abstraction is that a flying bit occupies some minimal volume, and that at most a constant number of flying bits can overlap in space at any time. To just ify constant speed o f signal propagat ion we note that information propagat ion th rough empty space or another inelaborate med ium is not much slower than the velocity of light in vacuum. Costly hardware is required for delaying the transfer of signals and we may be allowed to consider such arrangements as processors. It seems that a simple medium which transfers light considerably slowly will be extremely difficult to discover. I f this ever happens, the medium can serve as a gigantic storage device. The speed of a processor in the model can be variable, since processors can elect how often they wish to make a move. The fact that processors can move at speeds of up to that of t ransmit ted messages may seem unrealistic at the moment, but movement of comput ing devices at speeds which are a considerable fraction of the speed of light is not physically infeasible. To summarize, the main observations under ly ing the Spatial Machine model are: • Processors occupy some minimal amount of space. • Memory cells are essentially specifically p rog rammed processors. • Message bits travel th rough space at a bounded speed. • A finite region of empty space can have a bounded number of states. Consequently, the region can \"contain\" only a bounded number of bits at any moment . • Any specific comput ing system has finitely many processors and memory cells. Nevertheless, processors and messages can move in an unlimited, infinite, empty space. Cellular Automata capture most of these observations. In particular, moving processors can be simulated by a cellular automaton. Spatial Machines limit the number of \"comput ing devices\" to be finite and describe processor movement and message transfer in a more intuitive fashion. The model recaptures some of the Tur ing Machine's characteristics, such as polynomial vicinity and processor mobility. Al though current technology does not allow or exploit processor movement, except maybe outer space-based dist r ibuted networks, there is no physical justification to prohibi t mobility. Fur ther , if we do not stick to the tradit ional \"metallic\" notion o f a machine, we may encounter moving biological processors such as enzymes, animals, and humans. The Spatial Machine model is a imed at represent ing physically realizable machines ra ther than any specific technology. Relation to Other Models Models of computat ion A and B are said to be equivalent if for every instance of A there is an instance of B that accepts the same language and vice versa. In this section we draw the line between stationary and nonstationary Spatial Machines: Nonstationary Spatial Machines with two processors or more are equivalent to Tur ing Machines, and stationary Spatial Machines to Finite Automata. THEOREM 1. Any Turing Machine can be simulated by a two-processor Spatial Machine in O(T 2) time. Proof: Similar to Vitfinyi's simulation of a tape with a queue [15]. The simulating Spatial Machine has two processors P and R. The processor P simulates the finite control and the read/write head of the Turing Machine. The processor R functions as a reflector: any bit received at R from P's direction is reflected back. The empty cells between P and R are analogous to the cells on the tape of the Tur ing Machine. I f the input length is n, then initially the distance between P and R is 2n and the data loop (Figure 1) formed by the flying bits between P and R represents the input string which is assumed to be over the alphabet {0, 1}. The representat ion is four bits for each character allowing for a blank and special \"head location\" H and \"end of tape\" T designators. The idea is to keep the content of the tape on the fly in the data loop between P and R, moving P far ther from R when the tape requires extension. At any point in time, P holds in its state the value of three consecutive characters on the \"tape\" and the state o f the finite control of the simulated Tur ing Machine which we call the \"program state\" S. Let A, B, C designate any characters, b a blank, H head location, T end of tape, N the next character received, and W the character to be next written on the tape as assigned by the transit ion function of the Tur ing Machine. P repeats the following: • Suppose the state is ABC. Read four bits (N) while sending back A. • I f C # H then change state to BCN. • Else if the state is ABH (head designator jus t appeared) then: I f the next character received N is T (end of tape) then move the processor four cells to the left while sending B, and change state to HbT. -Otherwise , the transit ion function gives, as a function of the p rogram state S and N, the character W to replace N with, the movement of the head, and the next p rogram state. Change S to the next p rogram state, then: *If the head stays then change state to BHW. *If the head moves r ight then change state to BWH. *If the head moves left then change state to HBW. COMMUNICATIONSOFTHE ACM/October 1992/Vol.35, No.10 6? S P A T I A L MACHINES A simulation o f one step involves one loop over the \"tape.\" Hence, simulation time is O(T2). [] We now show how to simulate a Spatial Machine on a 3D Tur ing Machine. Let A be a Spatial Machine. Let the configuration of a cell be (s, ]), where s is the state of the processor if the cell contains one or empty if not, a n d f i s the value of the flying bits. Let ~ be the configuration (empty, < blank . . . . . blank > ). Let B ° = { r . . . . . r} 3 be a box enclosing all non-e cells in the initial setup of A. Let S be the finite set of possible configurat ions of a cell of A, with an addit ional e lement A. Define an a lphabet E = S × S × {in, out} and call the letter (~, A, out) a blank. Let T be a Tur ing Machine with a 3D tape and with the alphabet ]g. Following is a sketch of a simulation o f the Spatial Machine A by the Tur ing Machine T: • When start ing to simulate step t o f the Spatial Machine, each tape slot (i , j , k) will contain the letter (ct, A,/), where ct is the configurat ion o f Figure 2. Figure 1. cell (i, j , k) of A pr ior to step t, and where I is in if (i, j , k) is close enough to B ° to be considered (see below). Let B t be the set of slots marked in. • To simulate step t, T will go over all the tape slots in B t. For each such slot (i, j , k), T will calculate ct+ 1 for the cor responding cell of A, from the configurations ct o f the six neighbors o f the cell, which are embedded in the letters o f the corresponding tape slots, and write the letter (ct, ct+l) at the slot (i, j , k). T will then go again over B t, replace each letter (ct, Ct+l) with (ct+l, A), and mark all neighbors of elements of B t as in, thus forming B t+t. A Tur ing Machine with a 3D tape is computat ional ly equivalent (computes the same functions) to a single tape Tur ing Machine. Hence a nonstat ionary Spatial Machine is computat ional ly equivalent to a Tur ing Machine. THEOREM 2. A stationary Spatial Machine is equivalent to a Finite Automaton. Figure 3. Proof. Simulating a Finite Automaton by a Spatial Machine: the simulat

Spatial machines: a more realistic approach to parallel computation

The k-way graph partitioning problem can be transformed into the maximum k-cut problem using a proposed technique of graph modification. It is possible to transform the graph partitioning problem into the max-cut problem by incorporating node size information into the edge weight. After transformation, a very simple cost function can be devised which makes the proposed algorithm more efficient than the Kernighan-Lin (K-L) algorithm (1970). The computing time per iteration of the algorithm is O(k*N/sup 2/), where N is the number of nodes in the given graph. Experimental results show that the proposed algorithm outperforms the K-L algorithm both in the quality of solutions and in the elapsed time. Also, as the difference between the sizes of the nodes increases, the performance gap between the proposed algorithm and the K-L algorithm becomes larger. >

Computational Aspects of Vlsi

Citations

Optimal voltages and sizing for low power [CMOS VLSI]

Wait-free clock synchronization

Optimal Sorting on Multi-Dimensionally Mesh-Connected Computers

Spatial machines: a more realistic approach to parallel computation

An efficient k-way graph partitioning algorithm for task allocation in parallel computing systems

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