Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TLDR
In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.Abstract:
Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.read more
Citations
More filters
Patent
Heterojunction semiconductor device with element isolation structure
TL;DR: In this paper, an element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconducting layer are laminated in this order.
Journal ArticleDOI
Strain-Driven Mound Formation of Substrate under Epitaxial Nanoparticles
Tanya Gupta,James B. Hannon,Jerry Tersoff,Rudolf M. Tromp,John A. Ott,John Bruley,Daniel A. Steingart +6 more
TL;DR: It is proposed that relaxation of strain drives the mound formation of crystalline SiC nanoparticles, which involves a dramatic restructuring of the substrate, in striking contrast to the familiar scenario in which only the deposited material restructures to relieve strain.
Journal ArticleDOI
Improved CMOS performance via enhanced carrier mobility
TL;DR: In this paper, the electron and hole mobility in the transistors of Si complementary metal-oxide-silicon (CMOS) devices has been investigated and various approaches for achieving enhanced mobility in CMOS devices are discussed.
Book ChapterDOI
Electron Velocity in Sub-50-Nm Channel Mosfets
TL;DR: In this article, an inverse modeling of state-of-the-art NMOSFETs is used to investigate electron transport models and in particular to extract the effective velocity of electron injection from source to channel.
Journal ArticleDOI
Threshold voltage reduction in strained-Si/SiGe MOS devices due to a difference in the dielectric constants of Si and Ge
A.N.M. Zainuddin,Anisul Haque +1 more
TL;DR: In this paper, the authors show that a higher value of the dielectric constant in SiGe relative to that in Si causes a reduction in the magnitude of the threshold voltage in strained-Si/SiGe n- and p-MOSFETs.
References
More filters
Journal ArticleDOI
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Journal ArticleDOI
On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Journal ArticleDOI
Thermal and Electrical Properties of Heavily Doped Ge‐Si Alloys up to 1300°K
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI
Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.