Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TLDR
In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.Abstract:
Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.read more
Citations
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Journal ArticleDOI
Modeling of the Threshold Voltage in Strained $\hbox{Si/Si}_{1 - x} \hbox{Ge}_{x}/\hbox{Si}_{1 - y}\hbox{Ge}_{y}(x \geq y)$ CMOS Architectures
Y.L. Tsang,Sanatan Chattopadhyay,Suresh Uppal,Enrique Escobedo-Cousin,Hiran Ramakrishnan,Sarah H. Olsen,Anthony O'Neill +6 more
TL;DR: In this paper, an analytical model of threshold voltage for globally strained Si/SiGe CMOS devices using a dual channel architecture is proposed, and the model provides a physical insight for the variation of for both n- and p-MOSFETs in a dual-channel architecture, and it can be generalized to be applicable to single-channel devices as well.
Journal ArticleDOI
Thick-Strained-Si/Relaxed-SiGe Structure of High-Performance RF Power LDMOSFETs for Cellular Handsets
M. Kondo,Nobuyuki Sugii,Y. Hoshino,W. Hirasawa,Yoshinobu Kimura,M. Miyamoto,T. Fujioka,Shiro Kamohara,Y. Kondo,Shinichiro Kimura,I. Yoshida +10 more
TL;DR: In this paper, a strain-Si/relaxed-SiGe structure was applied to laterally diffused MOSFETs in order to improve the PAE of cellular handset RF power-amplifier applications.
Journal Article
Submicron mapping of strained silicon-on-insulator features induced by shallow-trench-isolation structures
TL;DR: In this paper, real-space maps of strain within silicon-on-insulator (SOI) features induced by adjacent, embedded shallow-trench-isolation (STI) SiO2 regions were obtained using x-ray microbeam diffraction.
Journal ArticleDOI
Measurement of in-plane and depth strain profiles in strained-Si substrates
Atsushi Ogura,Daisuke Kosemura,Kosuke Yamasaki,Satoshi Tanaka,Yasuto Kakemura,Akiko Kitano,Ichiro Hirosawa +6 more
TL;DR: In this paper, in-plane and depth strain profiles in commercial strained-Si substrates were evaluated by UV-Raman mapping and X-ray diffraction (XRD) techniques, showing that the strain at the edge region was larger than that in the center for the Bulk substrate, while the strain varied gradually from one side to the other side in the SGOI and strained-silicon-on-insulator (SSOI) substrates.
Journal ArticleDOI
Biaxially strained extremely-thin body In0.53Ga0.47As-on-insulator metal-oxide-semiconductor field-effect transistors on Si substrate and physical understanding on their electron mobility
Sanghyeon Kim,Masafumi Yokoyama,Ryosho Nakane,Osamu Ichikawa,Takenori Osada,Masahiko Hata,Mitsuru Takenaka,Shinichi Takagi +7 more
TL;DR: In this paper, the authors report the electrical characteristics of strained In0.53Ga0.47As-OI metal-oxide-semiconductor field effect transistors (MOSFETs) on Si substrates fabricated by a direct wafer bonding (DWB) technique.
References
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Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
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Journal ArticleDOI
Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates
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