Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TLDR
In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.Abstract:
Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.read more
Citations
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Proceedings ArticleDOI
SiGe-On-Insulator (SGOI): substrate preparation and MOSFET fabrication for electron mobility evaluation
Zhiyuan Cheng,Matthew T. Currie,Christopher W. Leitz,Gianni Taraschi,Arthur J. Pitera,Minjoo L. Lee,Thomas A. Langdo,J.L. Hoyt,Dimitri A. Antoniadis,Eugene A. Fitzgerald +9 more
TL;DR: In this article, the benefits of the conventional SOI technology and the SiGe technology have been combined to improve DC and RF performance using, the enhanced electronic properties associated with strain engineering and heterojunction energy barriers.
Journal ArticleDOI
Performance Improvement in Tensile-Strained $hbox In_0.5hbox Al_0.5hbox As/hbox In_xhbox Ga_1-xhbox As/hbox In_0.5hbox Al_0.5hbox As$ Metamorphic HEMT
TL;DR: In this article, the authors proposed a metamorphic high-electron mobility transistor with tensile-strained channel, which exhibits significant improvements in dc and RF characteristics, including extrinsic transconductance, current driving capability, thermal stability, unity-gain cutoff frequency, maximum oscillation frequency, output power, power gain, and power added efficiency.
Patent
SOI chip with recess-resistant buried insulator and method of manufacturing the same
Yee-Chia Yeo,Chenming Hu +1 more
TL;DR: A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate as mentioned in this paper, where active devices such as transistors and diodes can be formed in the semiconductor layer.
Patent
Strained Transistor with Optimized Drive Current and Method of Forming
TL;DR: In this article, a strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region, which can lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device.
References
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Journal ArticleDOI
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Journal ArticleDOI
On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Journal ArticleDOI
Thermal and Electrical Properties of Heavily Doped Ge‐Si Alloys up to 1300°K
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI
Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.