Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TLDR
In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.Abstract:
Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.read more
Citations
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Journal ArticleDOI
Strain measured in a silicon-on-insulator, complementary metal-oxide-semiconductor device channel induced by embedded silicon-carbon source/drain regions
TL;DR: In this paper, the strain imparted to 60 nm wide, silicon-on-insulator (SOI) channel regions by heteroepitaxially deposited, embedded silicon carbon (e-SiC) features was measured using x-ray microbeam diffraction, representing one of the first direct measurements of the lattice parameter conducted in situ in an SOI device channel.
Patent
Substrate having silicon germanium material and stressed silicon nitride layer
TL;DR: In this article, a stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate, and can be a tensile or compressively stressed layer according to the desired device characteristics.
Patent
Methods for forming a transistor and modulating channel stress
TL;DR: In this paper, methods for manufacturing transistors and altering the stress in the channel region of a single transistor are described. But the authors focus on the effect of the transistors on the channel.
Patent
Strained SOI MOSFET device and method of fabricating same
TL;DR: In this paper, a MOSFET device including a semiconductor substrate, an SiGe layer provided on top of the substrate, and an Si layer provided over the SiGe layers is described.
Journal ArticleDOI
Nanopatterning of Si/SiGe electrical devices by atomic force microscopy oxidation
TL;DR: In this article, two nanopatterning methods for silicon/silicon-germanium (Si/SiGe) heterostructures are demonstrated: (1) direct atomic force microscopy (AFM) oxidation on SiGe layers and (2) AFM oxidation on silicon followed by selective wet etching of SiGe.
References
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Journal ArticleDOI
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Journal ArticleDOI
On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Journal ArticleDOI
Thermal and Electrical Properties of Heavily Doped Ge‐Si Alloys up to 1300°K
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI
Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.