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Journal ArticleDOI

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

TLDR
In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract
Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

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Citations
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Journal ArticleDOI

Modelling of threshold voltage and subthreshold slope of strained-Si MOSFETs including quantum effects

TL;DR: In this article, the threshold voltage and sub-threshold slope of the strained-Si channel n-MOSFETs were determined, taking into account quantum-mechanical effects, and the effect of bandgap narrowing due to heavy channel doping and surface roughness at the Si/SiGe heterointerface for ultra thin channels.
Patent

MOSFET device with a strained channel

TL;DR: In this paper, an ultra-thin MOSFET device with a strained silicon channel on the underlying insulator layer is proposed. But the authors focus on the performance of the channel and do not consider the impact of biaxial tensile strain on the channel.
Journal ArticleDOI

Paramagnetic point defects at interfacial layers in biaxial tensile strained (100)Si/SiO2

TL;DR: In this paper, a comparative electron spin resonance study was performed on (100)Si/SiO2 entities, grown by thermal oxidation of biaxial tensile strained (sSi) layers, epitaxially grown on a strain relaxed Si0.8Ge0.2 buffer layer, and standard (100,Si.
Journal ArticleDOI

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

TL;DR: In this article, the basic methodologies and models used in the semi-classical modelling of CMOS transistors in the framework of the generalized scaling scenario are reviewed and compared to the experiments to assess the understanding of the underlying physics and the predictive capabilities.
References
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Journal ArticleDOI

Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys

TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Journal ArticleDOI

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Journal ArticleDOI

Thermal and Electrical Properties of Heavily Doped Ge‐Si Alloys up to 1300°K

TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Journal ArticleDOI

Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors

TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI

Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates

TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
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