Journal ArticleDOI
Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
Navab Singh,K.D. Buddharaju,Sanjeev Kumar Manhas,Ajay Agarwal,S.C. Rustagi,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
TLDR
The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.Abstract:
Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.read more
Citations
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Journal ArticleDOI
Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties
TL;DR: In this article, the authors summarized some of the essential aspects of silicon-nanowire growth and of their electrical properties, including the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs-Thomson effect for the silicon wire growth velocity.
Journal ArticleDOI
Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature
TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.
Journal ArticleDOI
HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture.
TL;DR: A bit- cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work.
Proceedings ArticleDOI
HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector
TL;DR: In this paper, a double-layer stacked HfOx vertical RRAM is demonstrated for 3D crosspoint architecture using a cost-effective fabrication process, and a unique write/read scheme is proposed for 3d cross-point architecture.
Journal ArticleDOI
Synthesis and modification of silicon nanosheets and other silicon nanomaterials.
TL;DR: This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications and a soft synthetic method for silicon nanOSheets with chemical surface modification in a solution process.
References
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Journal ArticleDOI
A general approach for the performance assessment of nanoscale silicon FETs
TL;DR: In this article, a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach") was proposed.
Proceedings ArticleDOI
Silicon Nanowire Arrays for Ultrasensitive Label-Free Detection of DNA
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Proceedings ArticleDOI
A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices
Hyunjin Lee,Seong-Wan Ryu,Jin-Woo Han,Lee-Eim Yu,Maesoon lm,Chimgjin Kim,Sungho Kim,Eujime Lee,Kuk-Hwan Kim,Ju-Hyun Kim,Dong-il Bae,Sang Cheol Jeon,Kwang Hee Kim,Gi Sung Lee,Jae Sub Oh,Yun Chang Park,Woo Ho Bae,Jung Jae Yoo,Jim Mo Yang,Hee Mok Lee,Yang-Kyu Choi +20 more
TL;DR: In this article, an 8 nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time.
Proceedings ArticleDOI
Gate Work Function Engineering for Nanotube-Based Circuits
TL;DR: The use of an Al-gate translates directly into a threshold-voltage shift relative to a Pd-gated FET, corresponding to the work function difference between the two metal gates.
Proceedings ArticleDOI
3D Stacked Nanowires CMOS Integration with a Damascene Finfet Process
Thomas Ernst,Cecilia Dupre,Erwan Dornel,Jean-Charles Barbe,S. Becu,C. Vizioz,Vincent Delaye,Francois Andrieu,J-M. Hartmann,Sébastien Barnola,Thierry Poiroux,O. Faynot,Gerard Ghibaudo,Simon Deleonibus +13 more
TL;DR: In this paper, a morphological and electrical demonstration of CMOS devices with 3 and 4 stacked nanowires (30 to 70 nm) was presented, which showed an up to 3.6 ION increase compared to a one-level trigate on SOI.