Journal ArticleDOI
Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
Navab Singh,K.D. Buddharaju,Sanjeev Kumar Manhas,Ajay Agarwal,S.C. Rustagi,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
TLDR
The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.Abstract:
Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.read more
Citations
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Journal ArticleDOI
Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties
TL;DR: In this article, the authors summarized some of the essential aspects of silicon-nanowire growth and of their electrical properties, including the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs-Thomson effect for the silicon wire growth velocity.
Journal ArticleDOI
Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature
TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.
Journal ArticleDOI
HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture.
TL;DR: A bit- cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work.
Proceedings ArticleDOI
HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector
TL;DR: In this paper, a double-layer stacked HfOx vertical RRAM is demonstrated for 3D crosspoint architecture using a cost-effective fabrication process, and a unique write/read scheme is proposed for 3d cross-point architecture.
Journal ArticleDOI
Synthesis and modification of silicon nanosheets and other silicon nanomaterials.
TL;DR: This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications and a soft synthetic method for silicon nanOSheets with chemical surface modification in a solution process.
References
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Proceedings ArticleDOI
High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability
Sung Dae Suk,Sung-young Lee,Sung-min Kim,Eun-Jung Yoon,Min-Sang Kim,Ming Li,Chang Woo Oh,Kyoung Hwan Yeo,Sung Hwan Kim,Dong-Suk Shin,Kwan-Heum Lee,Heungsik Park,Jeorig Nam Han,Choong-Hee Park,Jong-Bong Park,Dong-Won Kim,Donggun Park,Byung-Il Ryu +17 more
TL;DR: For the first time, a gate-all-around twin silicon nanowire transistor (TSNWFET) was successfully fabricated on bulk Si wafer using self-aligned damascene-gate process.
Proceedings ArticleDOI
5nm-gate nanowire FinFET
Fu-Liang Yang,Di-Hong Lee,Hou-Yu Chen,Chang-Yun Chang,Sheng-Da Liu,Cheng-Chuan Huang,Tang-Xuan Chung,Hung-Wei Chen,Chien-Chao Huang,Yi-Hsuan Liu,C.C. Wu,Chi-Chun Chen,Shih-Chang Chen,Ying-Tsung Chen,Ying-Ho Chen,C.H. Chen,Bor-Wen Chan,Peng-Fu Hsu,Jyu-Horng Shieh,Han-Jan Tao,Yee-Chia Yeo,Yiming Li,Jam-Wem Lee,Pu Chen,Mong-Song Liang,Chenming Hu +25 more
TL;DR: In this paper, a new nanowire FinFET structure was developed for CMOS device scaling into the sub-10 nm regime, and gate delay of 0.22 and 0.48 ps with excellent sub-threshold characteristics were achieved with very low off leakage cur-rent less than 10 nA/ /spl mu/m.
Journal ArticleDOI
DNA sensing by silicon nanowire: charge layer distance dependence.
Guo-Jun Zhang,Gang Zhang,Jay Huiyi Chua,Ru-Ern Chee,Ee Hua Wong,Ajay Agarwal,K.D. Buddharaju,Navab Singh,Zhiqiang Gao,N. Balasubramanian +9 more
TL;DR: To provide a comprehensive understanding of the field effect in silicon nanowire (SiNW) sensors, a systematic approach to fine tune the distance of a charge layer by controlling the hybridization sites of DNA to the SiNW preimmobilized with peptide nucleic acid (PNA) capture probes.
Journal ArticleDOI
Extremely scaled silicon nano-CMOS devices
Leland Chang,Yang-Kyu Choi,Daewon Ha,Pushkar Ranade,Shiying Xiong,Jeffrey Bokor,Chenming Hu,Tsu-Jae King +7 more
TL;DR: Key elements of silicon-based CMOS technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.
Journal ArticleDOI
Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires*
Yu Huang,Charles M. Lieber +1 more
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.