Journal ArticleDOI
Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs
TLDR
In this article, a new model for thermal resistance estimation in fin-shaped field effect transistors (FinFETs) and stacked-nanowire FETs was proposed.Abstract:
In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.read more
Citations
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Journal ArticleDOI
A Vertical Combo Spacer to Optimize Electrothermal Characteristics of 7-nm Nanosheet Gate-All-Around Transistor
TL;DR: In this article, the impact of self-heating effect (SHE) on nanosheet gate-all-around (GAA) transistor with a vertical combo spacer and different underlap/overlap channels is studied by the 3-D TCAD simulation.
Journal ArticleDOI
Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET
TL;DR: In this paper , the authors investigated the impact of ambient temperature and interface thermal contact resistance induced self heating effect in the stacked nanosheet field effect transistors (NS-FET) using extensive numerical simulations.
Journal ArticleDOI
Extraordinarily enhanced evaporation of water droplets on graphene-nanostructured coated surfaces
TL;DR: In this article, the authors investigated the application of graphene nanoplatelets (GNPs) coatings for the enhancement of evaporation of small sessile water droplets at sub-boiling temperatures.
Journal ArticleDOI
Experimental Evaluation of Self-Heating and Analog/RF FOM in GAA-Nanowire FETs
TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
Journal ArticleDOI
Study on Degradation Mechanisms of Thermal Conductivity for Confined Nanochannel in Gate-All-Around Silicon Nanowire Field-Effect Transistors
TL;DR: An analytical thermal conductivity model for confined nanochannel in gate-all-around silicon nanowire field effect transistors (GAA SiNW FETs) is developed by considering the limitations caused by the cross section and length as discussed by the authors.
References
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Journal ArticleDOI
Measurement and modeling of self-heating in SOI nMOSFET's
TL;DR: In this article, the authors measured and modeled self-heating in SOI nMOSFETs under static operating conditions and showed that the measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation.
Journal ArticleDOI
Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques
TL;DR: In this article, a new thermal extraction technique based on an analytically derived expression for the electro-thermal drain conductance in saturation is presented, which can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.
Journal ArticleDOI
SOI thermal impedance extraction methodology and its significance for circuit simulation
TL;DR: In this paper, the authors reported a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs, where the AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance and thermal capacitance associated with the SOI device.
Proceedings ArticleDOI
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin,Brian J. Greene,Shreesh Narasimha,J. Cai,A. Bryant,Carl J. Radens,Vijay Narayanan,Barry Linder,Herbert L. Ho,A. Aiyar,E. Alptekin,J-J. An,Michael V. Aquilino,Ruqiang Bao,V. Basker,Nicolas Breil,MaryJane Brodsky,William Y. Chang,Clevenger Leigh Anne H,Dureseti Chidambarrao,Cathryn Christiansen,D. Conklin,C. DeWan,H. Dong,L. Economikos,Bernard A. Engel,Sunfei Fang,D. Ferrer,A. Friedman,Allen H. Gabor,Fernando Guarin,Ximeng Guan,M. Hasanuzzaman,J. Hong,D. Hoyos,Basanth Jagannathan,S. Jain,S.-J. Jeng,J. Johnson,B. Kannan,Y. Ke,Babar A. Khan,Byeong Y. Kim,Siyuranga O. Koswatta,Amit Kumar,T. Kwon,Unoh Kwon,L. Lanzerotti,H-K Lee,W-H. Lee,A. Levesque,Wai-kin Li,Zhengwen Li,Wei Liu,S. Mahajan,Kevin McStay,Hasan M. Nayfeh,W. Nicoll,G. Northrop,A. Ogino,Chengwen Pei,S. Polvino,Ravikumar Ramachandran,Z. Ren,Robert R. Robison,Saraf Iqbal Rashid,Viraj Y. Sardesai,S. Saudari,Dominic J. Schepis,Christopher D. Sheraw,Shariq Siddiqui,Liyang Song,Kenneth J. Stein,C. Tran,Henry K. Utomo,Reinaldo A. Vega,Geng Wang,Han Wang,W. Wang,X. Wang,D. Wehelle-Gamage,E. Woodard,Yongan Xu,Y. Yang,N. Zhan,Kai Zhao,C. Zhu,K. Boyd,E. Engbrecht,K. Henson,E. Kaste,Siddarth A. Krishnan,Edward P. Maciejewski,Huiling Shang,Noah Zamdmer,R. Divakaruni,J. Rice,Scott R. Stiffler,Paul D. Agnello +98 more
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Proceedings ArticleDOI
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
Chetan Prasad,Lei Jiang,Dhruv Singh,M. Agostinelli,C. Auth,P. Bai,Travis Eiles,J. Hicks,Chia-Hong Jan,Kaizad Mistry,Sanjay Natarajan,B. Niu,Paul A. Packan,Daniel Pantuso,Ian R. Post,S. Ramey,A. Schmitz,Sell Bernhard,S. Suthram,J. Thomas,Curtis Tsai,P. Vandervoorn +21 more
TL;DR: In this article, the authors describe various measurements on self-heat performed on Intel's 22nm process technology and outline its reliability implications, comparing them to thermal modeling results and analytical data.