Showing papers on "Metal gate published in 2018"

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Abstract: Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.

Steep-Slope WSe2 Negative Capacitance Field-Effect Transistor

Abstract: P-type two-dimensional steep-slope negative capacitance field-effect transistors are demonstrated for the first time with WSe2 as channel material and ferroelectric hafnium zirconium oxide in gate dielectric stack. F4-TCNQ is used as p-type dopant to suppress electron leakage current and to reduce Schottky barrier width for holes. WSe2 negative capacitance field-effect transistors with and without internal metal gate structures and the internal field-effect transistors are compared and studied. Significant SS reduction is observed in WSe2 negative capacitance field-effect transistors by inserting the ferroelectric hafnium zirconium oxide layer, suggesting the existence of internal amplification (∼10) due to the negative capacitance effect. Subthreshold slope less than 60 mV/dec (as low as 14.4 mV/dec) at room temperature is obtained for both forward and reverse gate voltage sweeps. Negative differential resistance is observed at room temperature on WSe2 negative capacitance field-effect-transistors as the...

Cryogenic Temperature Characterization of a 28-nm FD-SOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration

Abstract: Silicon co-integration offers compelling scale-up opportunities for quantum computing. In this framework, cryogenic temperature is required for the coherence of solid-state quantum devices. This paper reports the characterization of an nMOS quantum-dot dedicated structure below 100 mK. The device under test is built in thin silicon film fabricated with 28 nm high- $k$ metal gate ultra-thin body and ultra-thin buried oxide advanced CMOS technology. The MOS structure is functional with improved performances at cryogenic temperature. The results open new research avenues in CMOS co-integration for quantum computing applications within the FD-SOI platform.

Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs

Abstract: In this paper, we systematically evaluate dc/ac performances of sub-7-nm node fin field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) using fully calibrated 3-D TCAD. The stress effects of all the devices were carefully considered in terms of carrier mobility and velocity averaged within the active regions. For detailed AC analysis, the parasitic capacitances were extracted and decomposed into several components using TCAD RF simulation platform. FinFETs improved the gate electrostatics by decreasing fin widths to 5 nm, but the fin heights were unable to improve RC delay due to the trade-off between on-state currents and gate capacitances. The NSFETs have better on-state currents than do the FinFETs because of larger effective widths (Weff) under the same device area. Particularly p-type NSFETs have larger compressive stress within the active regions affected by metal gate encircling all around the channels, thus improving carrier mobility and velocity much. On the other hand, the NSFETs have larger gate capacitances because larger Weff increase the gate-to-source/drain overlap and outerfringing capacitances. In spite of that, sub-7-nm node NSFETs attain better RC delay than sub-7-nm node as well as 10-nm node FinFETs for standard and high performance applications, showing better chance for scaling down to sub-7-nm node and beyond.

Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

Abstract: We report on vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs, integrated in a CMOS dual Work Function Metal Replacement Metal Gate (RMG) flow. The integration of a lower temperature STI module and a SiN liner, designed to mitigate the oxidation-induced NW size loss and improve the width/height aspect ratio and NW controllability, is validated electrically. Additionally, Si GAA devices with reduced vertical nanowire spacing are demonstrated. The challenges in terms of Work Function Metal thickness scaling are highlighted, and a thinner nMetal process with low V TH capability and no J G /PBTI lifetime penalty is proposed. Electrically, these process innovations lead to a large improvement of I ON /I OFF performance and short channel margin. Finally, a ring oscillator circuit demonstration is shown, with a improvement of gate delay from 24ps down to 10ps at matched V DD demonstrated.

Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory

Abstract: For the first time we propose a 28nm FDSOI e-NVM solution for automotive micro-controller applications using a Phase Change Memory (PCM) based on chalcogenide ternary material. A complete array organization is described exploiting body biasing capability of Fully Depleted Silicon On Insulator (FDSOI) transistors. Leveraging triple gate oxide integration with high-k metal gate (HKMG) stack, a true 5V transistor with high analog performance has been demonstrated. Reliable PCM 0,036um2 analytical cell with 2 decades programming window after 1 Million of cycles has been demonstrated. Finally, current distributions based on a fully integrated 16MB macro-cell is presented achieving Bit Error Rate (BER) < 10−8 after multiple bakes at 150°C and 10k cycling of code storage memory.

Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process

Abstract: In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high- k /metal gate FinFET flow are implemented to fabricate the GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H2 baking and oxidation methods in the RMG process. The proposed methods would increase the process thermal budget and improve film quality for the NW channels. Providing both structural and process advantages, the optimized devices with $L_{g} = 16$ nm demonstrate superb short-channel effect (SCE) immunity characteristics, with SS = 61.86$ mV/dec and DIBL = 6.5 mV/V for the inverted droplet NW device; these results are very close to the ideal limits of MOSFETs. The results also indicate that the inverted droplet NW devices have a slightly better SCE control than the circular NWs of similar geometric size.

Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

Abstract: For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high- $\kappa$ metal gate process and self-aligned-contacts. Back-biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.

Nonideality of Negative Capacitance Ge Field-Effect Transistors Without Internal Metal Gate

Abstract: We demonstrate negative capacitance (NC) Ge field-effect transistors (FETs) utilizing the TaN/HfZrO x /SiO2 gate stack. Typical characteristics of NC transistors, including the sub-60 mV/decade subthreshold swing (SS), the gate capacitance ${C} _{G}$ peak, and the negative differential resistance effect are achieved in NC Ge FETs without internal metal gate. Significant ${C} _{\textit {G}}$ peak, as the evidence of NC effect is obtained in NC transistors at the frequency up to MHz. Ferroelectric Ge FETs with counterclockwise ${I} _{\text {DS}} - {V} _{\text {GS}}$ loops due to trapping/detrapping, opposite hysteresis to the NC switching are also observed. The NC transistor has much steeper SS compared to the device dominated by the trapping/detrapping process. Statistical results show that only 10% of devices are dominated by the NC effect, and the density of defects in ferroelectric needs to be reduced to improve the yield of NC transistors.

Ultralow Defect Density at Sub-0.5 nm HfO2/SiGe Interfaces via Selective Oxygen Scavenging.

Abstract: The superior carrier mobility of SiGe alloys make them a highly desirable channel material in complementary metal-oxide-semiconductor (CMOS) transistors. Passivation of the SiGe surface and the associated minimization of interface defects between SiGe channels and high-k dielectrics continues to be a challenge for fabrication of high-performance SiGe CMOS. A primary source of interface defects is interfacial GeOx. This interfacial oxide can be decomposed using an oxygen-scavenging reactive gate metal, which nearly eliminates the interfacial oxides, thereby decreasing the amount of GeOx at the interface; the remaining ultrathin interlayer is consistent with a SiOx-rich interface. Density functional theory simulations demonstrate that a sub-0.5 nm thick SiOx-rich surface layer can produce an electrically passivated HfO2/SiGe interface. To form this SiOx-rich interlayer, metal gate stack designs including Al/HfO2/SiGe and Pd/Ti/TiN/nanolaminate (NL)/SiGe (NL: HfO2–Al2O3) were investigated. As compared to the...

Modeling Channel Length Scaling Impact on NBTI in RMG Si p-FinFETs

Abstract: Negative Bias Temperature Instability (NBTI) stress and recovery time kinetics fromReplacement Metal Gate (RMG) High-K Metal Gate (HKMG) p-channel FinFETs are measured and modeled. The impact of channel length (L) scaling on shift in threshold voltage ($\mathrm{V}_{T})$,its power-law time exponent (n), Voltage Acceleration Factor (VAF) and Temperature (T) activation $( \mathrm{E}_{A})$ is analyzed. TCAD and band structure calculations are utilized to explain the L dependence of experimental data.

Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Abstract: We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- ${k}$ metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.

Modeling of Process (Ge, N) Dependence and Mechanical Strain Impact on NBTI in HKMG SiGe GF FDSOI p-MOSFETs and RMG p-FinFETs

Abstract: A physical framework is used to model time kinetics of Negative Bias Temperature Instability (NBTI) in Si and SiGe FDSOI p-MOSFETs and p-FinFETs. The effects of Germanium (Ge%) in the channel and Nitrogen (N%) in the High-K Metal Gate (HKMG) gate stack are explained. Mechanical strain effects in terms of STI to active distance (SA) for FDSOI and channel length (L) scaling for FinFET are explained. Band structure is calculated to correlate the process (Ge%, N%, strain) impact on device degradation. The model is included in Sentaurus Device TCAD to predict NBTI kinetics in Si and SiGe FinFETs.

Impact of gate material engineering on ED-TFET for improving DC/analogue-RF/linearity performances

Abstract: To avoid the fabrication complexity and cost of nanoscale devices, a dual metal gate (DMG) in polarity controlled electrically doped tunnel field-effect transistor (ED-TFET) has been introduced first time for DC, analogue/radio frequency (RF) and linearity performance improvement. The formation of n+ drain and p+ source regions are done by applying polarity biases of PG-1 as 1.2 V and PG-2 as −1.2 V, respectively, over the silicon body in DMG-ED-TFET. Different analogue/RF and linearity performance metrics of DMG-ED-TFET are evaluated using ATLAS device simulator and compared with that of ED-TFET. The figure of merits (FOMs) studied in this work for DMG-ED-TFET are in terms of transconductance, gate-to-drain capacitance, gain bandwidth product, cut-off frequency and linearity parameters such as third-order transconductance coefficient ( g m 3 ), VIP3, IIP3 and IMD3. From the simulations, it is found that DMG-ED-TFET achieves significant improvement in these FOMs as compared to ED-TFET due to introduction of dual metal at gate electrode (gate workfunction engineering). The work has also optimised the proposed device to attain optimum analogue/RF and linearity performance.

Dielectric Modulated Triple Metal Gate All Around MOSFET (TMGAA)for DNA Bio-Molecule Detection

Abstract: Dielectric Restrained Triple Metal Gate All Around (TG GAA)MOSFET is investigated as a bio-sensor to nail its applicability in biomedical field for DNA molecule and neutral species detection in particular proteins (Biotin & Streptavidin). In this paper nanoparticle with different bio molecular concentrations and different permittivity have been inserted in the cavity inside the oxide layer. The mutation in the drain current (Ids)and the threshold voltage (vth)is then studied in order to assimilate the sensitivity of the MOSFET. The performance of Triple Metal Gate All Around (TG GAA)MOSFET has been compared with that of Dual Metal Gate All Around (DG GAA)MOSFET and Single Metal Gate All Around (SG GAA)MOSFET. Nanogap Embedded TGGAA MOSFET is advantageous from the integration point of view due to the compatibility with CMOS process of the forthcoming silicon based Lab on Chip Systems as well as increased sensitivity.

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

Abstract: 3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.

A Novel Gate-Normal Tunneling Field-Effect Transistor With Dual-Metal Gate

Abstract: In this combined experiment and simulation study we investigate a SiGe/Si based gatenormal tunneling field-effect transistor (TFET) with a pillar shaped contact to the tunneling junction which brings forth two significant advantages. The first, is improved electrostatics at the boundary of the tunneling junction which helps to diminish the influence of adverse tunneling paths, and thus, substantially sharpens the device turn on. The second, is a simplified fabrication of a dual-metal gate using a selfaligned process. We demonstrate the feasibility of the process and show the positive effect of a dual-metal gate in experiment. Overall the paper provides general guidelines for the improvement of the subthreshold swing in gate-normal TFETs which are not restrained to the material system.

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

Abstract: 3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

Impact of the Metal-Gate Material Properties in FinFET (Versus FD-SOI MOSFET) on High- $\kappa$ /Metal-Gate Work-Function Variation

Abstract: The 3-D technology computer-aided design simulations were performed with four metal-gate materials (i.e., titanium nitride, tungsten nitride, tantalum nitride, and molybdenum nitride) to quantitatively estimate the magnitude of work-function variation (WFV)-induced threshold-voltage variation (WFV-induced $\sigma {V}_{\mathrm{TH}}$ ) in high- $\kappa $ /metal-gate (HK/MG) MOSFETs [e.g., fin-shaped field-effect transistor (FinFET) and fully depleted silicon-on-insulator MOSFETs]. We found that the extended gate area effect in FinFETs extensively varied depending on the gate materials used. In order to substantially suppress the WFV-induced $\sigma {V}_{\mathrm{TH}}$ in HK/MG complementary metal–oxide–semiconductor technology, a new metal-gate material with the following characteristics should be developed: 1) higher standard deviation of probability for all grains and 2) lower standard deviation of WF values for all grains.

Analysis of DC Self Heating Effect in Stacked Nanosheet Gate-All-Around Transistor

Abstract: In this paper, self-heating effect in newly introduced stacked nanosheet gate-all-around transistor is investigated and discussed, and several architecture parameters such as metal gate thickness, number of channels, thermal conductivity of ILD and channel thickness affecting thermal reliability of nanosheet FET are studied through simulations. It is illustrated that nanosheet FET shows great lattice temperature variations and thermal resistance fluctuations from changes in such architecture parameters, and these can be mitigated by increasing thermal conductivity of ILD, and metal gate thickness.

Replacement metal gate patterning for nanosheet devices

Abstract: This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond

Abstract: In this paper, we propose the extendibility of ultra-thin body and box (UTBB) devices to 7 and 5 nm technology nodes focusing on electrostatics. A difficulty in scaling traditional UTBB is the need for SOI scaling to about one fourth of the gate length. We propose a U-channel fully depleted silicon on insulator architecture that starts off with a thicker SOI (8–11 nm) and has a U-shaped channel enabled by a recessed metal gate. This device improves the electrostatics by increasing the overall gate length at fixed metal gate opening, mitigating drain field coupling to the source due to the recessed metal gate region and having thin SOI below the center of the device (4–5 nm). Modeling shows that good electrostatics can be maintained at small metal gate opening to enable pitch scaling. This device provides lower cost options for mobile and IOT technologies.

Study of fully-depleted Ge double-gate n-type Tunneling Field-Effect Transistors for improvement in on-state current and sub-threshold swing

Abstract: In this paper, a fully-depleted (FD) Ge double-gate (DG) n-type Tunneling Field-Effect Transistors (TFET) structure is studied in detail by two-dimensional numerical simulation. The simulation results indicated that the on-state current Ion and on-off ratio of the FD Ge DG-TFET increases about 1 order of magnitude comparing with the Conventional Ge DG-TFET, and Ion=3.95×10-5 A/μm and the below 60 mV/decade subthreshold swing S=26.4 mV/decade are achieved with the length of gate LD=20 nm, the workfuntion of metal gate Φm=0.2 eV and the doping concentration of n+-type-channel ND=1×1018 cm-3. Moreover, the impacts of Φm, ND and LD are investigated. The simulation results indicated that the off-state current Ioff includes the tunneling current at the middle of channel IB the gated-induced drain leakage (GIDL) current IGIDL. With optimized Φm and ND, Ioff is reduced about 2 orders of magnitude to 2.5×10-13 A/μm with LD increasing from 40 nm to 100 nm, and on-off ratio is increased to 1.58×107.

Variability Predictions for the Next Technology Generations of n-type SixGe1-x Nanowire MOSFETs.

Abstract: Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on Si x Ge 1 − x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from s p 3 d 5 s ∗ tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.

Effect of gate dielectric on electrical parameters due to metal gate WFV in n-channel Si step FinFET

Abstract: This work reports the statistical impact of dielectric constant (k) of gate dielectric materials on various electrical parameters in step-FinFET (fin field-effect transistor) and conventional FinFET (C-FinFET) due to the gate metal work function variability (WFV). 3D technology computer-aided design simulations showed that several performance parameters are more affected by the WFV in C-FinFET than in step-FinFET. It was observed that the fluctuation of parameters like subthreshold swing (σSS), on current (σI on), and off current (σI off) are noticeably affected by dielectric materials. However, for both the structures, there is no significant variation in the threshold voltage (σV T) with variation in k values for varying grain size.

Preparation method and structure of three-dimensional memory

Abstract: The invention provides a preparation method and a structure of a three-dimensional memory According to the preparation method and the structure, a contact hole technology of a peripheral circuit region is advanced to be prior to a metal gate technology of an array memory region, so that etching of a contact hole to release of silicon oxide film stress of the peripheral circuit region is realized,distribution of macroscopic stress of a wafer is improved, and bending is effectively reduced In addition, the contact hole technology of the peripheral circuit region is arranged prior to the metalgate technology of the array memory region, so that nonuniformity of local stress of the metal gate technology of the array memory region cannot cause contact failure of a peripheral circuit The preparation method and the structure are realized by the following technical schemes

Performance Enhanced Unsymmetrical FinFET and its Applications

Abstract: A steep subthershold slope novel usymmetrical FinFET is proposed for gate lenght 9nm with improved performance in terms of I on /I off ratio in comparison to existing symmetrical structure. Proformance is furture optimised in terms of doping variations and under lap behaviour of FinFET. High-K dielectric material oxide and metal gate contact of high work function incorporated and performance compared. pFinFET and nFinFET both simulated togather to obtain ideal characteristics required to match in CMOS technology. 2D/3D Visual TCAD device simulator utilised in design of all FinFET structures.

Semiconductor device and method for fabricating the same

Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers An opening is formed in the ILD layer by etching A dielectric filling layer is formed in the opening By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers A conductive material is formed over the exposed source/drain epitaxial layers

TaN Versus TiN Metal Gate Input/Output pMOSFETs: A Low-Frequency Noise Perspective

Abstract: It is shown that replacing a TiN effective work function metal by TaN results in a pronounced reduction of the low-frequency noise power spectral density (PSD) of thick-SiO2 input/output (I/O) DRAM peripheral pMOSFETs. The 1/ $f$ noise is originating from carrier number fluctuations, suggesting that the observed reduction results from a decrease of the oxide trap density in the SiO2. On the other hand, I/O pMOSFETs with a TiN gate deposited by different methods or used as a sacrificial gate in a gate replacement integration scheme yield a similar high 1/ $f$ noise PSD and corresponding oxide trap density.