Showing papers by "STMicroelectronics published in 2016"

Roadmap on silicon photonics

Abstract: Silicon photonics research can be dated back to the 1980s. However, the previous decade has witnessed an explosive growth in the field. Silicon photonics is a disruptive technology that is poised to revolutionize a number of application areas, for example, data centers, high-performance computing and sensing. The key driving force behind silicon photonics is the ability to use CMOS-like fabrication resulting in high-volume production at low cost. This is a key enabling factor for bringing photonics to a range of technology areas where the costs of implementation using traditional photonic elements such as those used for the telecommunications industry would be prohibitive. Silicon does however have a number of shortcomings as a photonic material. In its basic form it is not an ideal material in which to produce light sources, optical modulators or photodetectors for example. A wealth of research effort from both academia and industry in recent years has fueled the demonstration of multiple solutions to these and other problems, and as time progresses new approaches are increasingly being conceived. It is clear that silicon photonics has a bright future. However, with a growing number of approaches available, what will the silicon photonic integrated circuit of the future look like? This roadmap on silicon photonics delves into the different technology and application areas of the field giving an insight into the state-of-the-art as well as current and future challenges faced by researchers worldwide. Contributions authored by experts from both industry and academia provide an overview and outlook for the silicon waveguide platform, optical sources, optical modulators, photodetectors, integration approaches, packaging, applications of silicon photonics and approaches required to satisfy applications at mid-infrared wavelengths. Advances in science and technology required to meet challenges faced by the field in each of these areas are also addressed together with predictions of where the field is destined to reach.

A SPAD-Based QVGA Image Sensor for Single-Photon Counting and Quanta Imaging

Abstract: A CMOS single-photon avalanche diode (SPAD)-based quarter video graphics array image sensor with 8- $\mu \text{m}$ pixel pitch and 26.8% fill factor (FF) is presented. The combination of analog pixel electronics and scalable shared-well SPAD devices facilitates high-resolution, high-FF SPAD imaging arrays exhibiting photon shot-noise-limited statistics. The SPAD has 47 counts/s dark count rate at 1.5 V excess bias (EB), 39.5% photon detection probability (PDP) at 480 nm, and a minimum of 1.1 ns dead time at 1 V EB. Analog single-photon counting imaging is demonstrated with maximum 14.2-mV/SPAD event sensitivity and 0.06e− minimum equivalent read noise. Binary quanta image sensor (QIS) 16-kframes/s real-time oversampling is shown, verifying single-photon QIS theory with $4.6\times $ overexposure latitude and 0.168e− read noise.

Silicon Photonics R&D and Manufacturing on 300-mm Wafer Platform

Abstract: Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated.

Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

Abstract: We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both single photon counting (SPC) intensity, and time resolved imaging. The 128×120 prototype has a pixel pitch of 7.83 μm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond connection [1]. The SPAD exhibits a median dark count rate (DCR) below 200cps at room temperature and 1V excess bias, and has a peak photon detection probability (PDP) of 27.5% at 640nm and 3 V excess bias.

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Abstract: We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.

Polymeric microneedles based enzymatic electrodes for electrochemical biosensing of glucose and lactic acid

Abstract: Polymeric microneedles (MNs) based working electrodes are fabricated by standard photolithography of poly(ethylene glycol) diacrylate (PEGDA) doped by enzyme, redox mediator and photoinitiator. This flexible device acts as working electrode in electrochemical detection of glucose and lactic acid in solution when glucose oxidase (GOx) and lactose oxidase (LOx) enzymes, respectively, are used. Biosensor showed a linear response in the ranges from 0 to 4 mM and from 0 to 1 mM, for glucose and lactic acid, respectively. A limit of detection equal to 1 μM is found. The developed technology has been patented.

A memetic algorithm to solve an unrelated parallel machine scheduling problem with auxiliary resources in semiconductor manufacturing

Abstract: In this paper, we propose a metaheuristic for solving an original scheduling problem with auxiliary resources in a photolithography workshop of a semiconductor plant. The photolithography workshop is often a bottleneck, and improving scheduling decisions in this workshop can help to improve indicators of the whole plant. Two optimization criteria are separately considered: the weighted flow time (to minimize) and the number of products that are processed (to maximize). After stating the problem and giving some properties on the solution space, we show how these properties help us to efficiently solve the problem with the proposed memetic algorithm, which has been implemented and tested on large generated instances. Numerical experiments show that good solutions are obtained within a reasonable computational time.

Experimental and Numerical Analysis of Hole Emission Process From Carbon-Related Traps in GaN Buffer Layers

Abstract: The role of carbon-related traps in GaN-based ungated high-electron mobility transistor structures has been investigated both experimentally and by means of numerical simulations. A clear quantitative correlation between the experimental data and numerical simulations has been obtained. The observed current decrease in the tested structure during backgating measurements has been explained simply by means of a thermally activated hole-emission process with $E_{A} = 0.9$ eV, corresponding to the distance of the acceptor-like hole-trap level from the GaN valence band. Moreover, it has been demonstrated by means of electrical measurements and numerical simulations that only a low percentage of the nominal carbon doping levels induces the observed current reduction when negative substrate bias is applied to the tested structure.

Reliable 300 mm Wafer Level Hybrid Bonding for 3D Stacked CMOS Image Sensors

Abstract: 3D Stacked Image sensor is the stacking of a Back-Side Illuminated (BSI) CMOS Image Sensor on a logic die. It enables compact size, higher performances and additional functionalities compared to standard BSI sensors. The highest footprint reduction is obtained with 3D hybrid bonding with metal interconnects between top and bottom tiers. Hybrid bonding process with oxide / copper direct bonding allows the highest scalability of interconnect pitch. In this study we present the morphological and electrical characterizations of a test vehicle. The hybrid bonding of wafers from two different technology nodes is performed using a dual damascene integration for the hybrid bonding level. The main parameters to assess the bonding interface quality are analyzed such as the influence of the pad design, the impact of reworkability and wafer -- to-wafer overlays. The process robustness is studied through reliability tests and electromigration measurements.

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

Abstract: Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when generating test programs for on-line execution; (2) it proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts; (3) it is providing guidelines for allowing the coexistence of the Core Self-Test library with the mission application while guaranteeing execution robustness. The proposed methodology has been experimented on a large industrial case study. The coverage level reached after one year of team work is over 87 percent of stuck-at fault coverage, and execution time is compliant with the ISO26262 specification. Experimental results suggest that alternative approaches may request excessive evaluation time thus making the generation flow unfeasible for large designs.

A Fully Integrated 320 GHz Coherent Imaging Transceiver in 130 nm SiGe BiCMOS

Abstract: A 320 GHz fully integrated terahertz imaging system is reported. The system is composed of a phase-locked high-power transmitter and a coherent high-sensitivity subharmonic-mixing receiver, which are fabricated using a 130 nm SiGe BiCMOS technology ( $f_{T}/f_{\max } = $ 220/280 GHz). To enhance the imaging sensitivity, a heterodyne coherent detection scheme is utilized. To obtain frequency coherency, fully integrated phase-locked loops are implemented on both the transmitter and receiver chips. According to the measurement results, consuming a total dc power of 605 mW, the transmitter chip achieves a peak radiated power of 2 mW and a peak EIRP of 21.1 dBm. The receiver chip achieves an equivalent incoherent responsivity of more than 7.26 MV/W and a sensitivity of 70.1 pW under an integration bandwidth of 1 kHz, with a total dc power consumption of 117 mW. The achieved sensitivity with this proposed coherent imaging transceiver is around ten times better compared with other state-of-the-art incoherent imagers. To the best of our knowledge, this paper demonstrates the first fully integrated coherent terahertz imaging transceiver on silicon.

A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

Abstract: Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human–Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from −1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range −40 °C to 120 °C exploiting −1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors with comparable performance, including those implemented in 28 nm technology, our platform provides 1.4× to 3.7× better energy efficiency.

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

Abstract: This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

Beam Switching Conformal Antenna Array for mm-Wave Communications

Abstract: In this letter, the design and measurement results of a millimeter-wave beam switching antenna are presented. Several antenna prototypes have been fabricated and measured in planar and conformal installations. The developed prototype consists of three antenna arrays of 16 patch elements in each array and it is operating at 61 GHz with linear polarization. A single-pole three-throw semiconductor switch is attached to the manufactured prototype using copper pillar attachment. The main beam direction of the convex antenna can be changed by switching between the antenna arrays in the prototype. Half sphere 3-D radiation pattern measurements have been performed. For the convex prototype, bent on the cylinder with radius 25 mm, beam switching with ${-{\hbox {32}}^\circ / + {\hbox {34}}^\circ} $ degrees is achieved.

A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture

Abstract: A 2.4 GHz interferer-resilient wake-up receiver for ultra-low power wireless sensor nodes uses an uncertain-IF dual-conversion topology, combining a distributed multi-stage N-path filtering technique with an unlocked low-Q resonator-referred local oscillator. This structure provides narrow-band selectivity and strong immunity against interferers, while avoiding expensive external resonant components such as BAW resonators or crystals. The 65 nm CMOS receiver prototype provides a sensitivity of −97 dBm and a carrier-to-interferer ratio better than −27 dB at 5 MHz offset, for a data rate of 10 kb/s at a 10−3 bit error rate, while consuming 99 $\mu \text{W}$ from a 0.5 V voltage supply under continuous operation.

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

Abstract: For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI

Abstract: This work demonstrates a fully-integrated, compact body-bias generator (BBG) with a fine voltage step and sub-100ns response time for use in process and voltage compensation as well as dynamic energy optimization. The generator is implemented in 28nm UTBB FDSOI, using only 1.0V core and 1.8V IO voltage inputs. A modular design enables easy integration into target mobile SoCs, scalable to power domains of any size. The fine resolution (5mV V th ), 100ns full-scale and 5ns incremental step response, low power ( CORE change is demonstrated experimentally.

A 234–261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4–7.2 dBm Output Power, 1.3% DC-to-RF Efficiency, and 1-GHz Divided-Down Output

Abstract: A 234–261-GHz signal source with record 7.2-dBm output power at 240 GHz and −105 dBc/Hz phase noise at 10-MHz offset is reported. Fabricated in a production 55-nm SiGe BiCMOS process with HBT ${f}_{\mathrm {T}}/{f}_{\mathrm {MAX}}$ of 330/350 GHz, the circuit includes a 120-GHz fundamental frequency VCO with 1.2-V AMOS varactors, a broadband MOS-HBT cascode LO tree driving a divide-by-128 chain, and a doubler with a record drain efficiency of 11.9%. The total power consumption of the signal source is 386 mW resulting in a DC-to-RF efficiency of 1.3%. A detailed discussion of the candidate LO-tree and doubler topologies and of the design methodology, which capitalizes on the MOS-HBT cascode and unique features of the 55-nm SiGe BiCMOS process, is provided.

Effects of Annealing Treatments on the Properties of Al/Ti/p-GaN Interfaces for Normally OFF p-GaN HEMTs

Abstract: This paper reports on the behavior of Al/Ti/p-GaN interfaces as gate contacts for p-GaN/AlGaN/GaN normally off high electron mobility transistor (HEMTs), highlighting the impact of the thermal budget on the metal gate on the device characteristics. In fact, while the devices subjected to an annealing at 800 °C show a considerable high leakage current, those with nonannealed Al/Ti gate contacts exhibit a normally off behavior, with a pinch-off voltage $V_{\mathrm {po}}= +1.1$ V and an on/off current ratio of $3 \times 10^{8}$ . Temperature-dependent electrical measurements on back-to-back Schottky diodes allowed to determine a Schottky barrier height $\Phi _{B}$ of 2.08 and 1.60 eV, for the nonannealed and 800 °C annealed gate contacts, respectively. Hence, the increase in the leakage current observed upon annealing at 800 °C was attributed to the lowering of the Schottky barrier height $\Phi _{B}$ of the metal gate. The interfacial structural characterization explained the barrier lowering induced by the annealing. This scenario was discussed through the simulated band diagram of the heterostructures, considering the experimental values of $\Phi _{B}$ . These results provide useful information for the device makers to optimize the fabrication flow of normally off HEMTs with p-GaN gate.

Global Registration of 3D Point Sets via LRS Decomposition

Abstract: This paper casts the global registration of multiple 3D point-sets into a low-rank and sparse decomposition problem. This neat mathematical formulation caters for missing data, outliers and noise, and it benefits from a wealth of available decomposition algorithms that can be plugged-in. Experimental results show that this approach compares favourably to the state of the art in terms of precision and speed, and it outperforms all the analysed techniques as for robustness to outliers.

Design and Implementation of an Integrated Reconfigurable Silicon Photonics Switch Matrix in IRIS Project

Abstract: This paper aims to present the design and the achieved results on a CMOS electronic and photonic integrated device for low cost, low power, transparent, mass-manufacturable optical switching. An unprecedented number of integrated photonic components (more than 1000), each individually electronically controlled, allows for the realization of a transponder aggregator device which interconnects up to eight transponders to a four direction colorless-directionless-contentionless ROADM. Each direction supports 12 200-GHz spaced wavelengths, which can be independently added or dropped from the network. An electronic ASIC, 3-D integrated on top of the photonic chip, controls the switch fabrics to allow a complete and microsecond fast reconfigurability.

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Abstract: Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonic-packaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

Tag, related method and system for identifying and/or authenticating objects

Abstract: A tag adapted to be applied to an object is disclosed. The tag includes a wireless communication interface, a processor and a memory. A univocal code, a cipher key and a count value are store in the memory. The tag generates a dynamic code as a function of the cipher key and the count value. Next, the tag varies the count value according to a determined operation, and stores the varied count value in the memory. The tag transmits the univocal code and the dynamic code to a reader device. The tag may transmit the univocal code and the dynamic code in a URL.

Tungsten and cobalt metallization: A material study for MOL local interconnects

Abstract: Middle-of-the-line (MOL) interconnect and contact resistances represent significant impacts to high-end IC performance at ≤ 10 nm nodes. CVD W-based metallization has been used for all nodes since the inception of damascene. However, it is now being severely challenged due to limited scaling of the traditional PVD Ti/CVD TiN barrier and ALD nucleation layers. This study reports the use of alternate barriers, along with metal-to-metal contact interface cleans, to reduce contact resistance for W-based MOL metallization. As well, we report the first use of Co metal for MOL contacts and local interconnects, with successful integration below a Cu BEOL dual damascene V0/M1 module. Metal line resistances are compared among the various options, and the challenges with each option are highlighted.