NEC

About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.

Semiconductor device and manufacturing method thereof

Abstract: A semiconductor device includes: a silicon substrate; and a field effect transistor including a gate insulating film over the silicon substrate, a gate electrode on the gate insulating film, and source and drain regions. The gate electrode includes, in part in contact with the gate insulating film, a crystallized Ni silicide region containing an impurity element of a conductivity type opposite to a conductivity type of a channel region in the field effect transistor.

Process for fabricating three-dimensional semiconductor device

Abstract: A process of fabricating a three-dimensional semiconductor device, comprising the steps of preparing at least two multilayer structures each including at least one semiconductor element and a conductor connected at one end to the semiconductor element and having at the other end an exposed surface, at least one of the multilayer structures further including a thermally fusible insulating adhesive layer having a surface coplanar with the exposed surface of the conductor, positioning the multilayer structures so that the exposed surfaces of the respective conductors of the multilayer structures are spaced apart from and aligned with each other, moving at least one of the multilayer structures with respect to the other until the exposed surfaces of the conductors of the multilayer structures contact each other, and heating the multilayer structures for causing the insulating adhesive layer of at least one of the multilayer structures to thermally fuse to the other multilayer structure with the semiconductor elements electrically connected together.

Multiservices medium access control protocol for wireless ATM system

Abstract: A medium access control (MAC) layer protocol is used in a wireless ATM system for integrated support of ATM services, including constant bit-rate (CBR), variable bit-rate (VBR) and available bit-rate (ABR) services. The MAC protocol supports both connectionless packet and connection-oriented virtual circuit modes, with appropriate service parameter and quality-of-services selection. A dynamic time division, multiple access/time division multiplex (TDMA/TDM) approach accommodates the service classes in an integrated manner. A supervisory MAC procedure integrates ATM ABR/VBR/CBR virtual circuits, providing burst-by-burst allocation of ABR cells and call-by-call allocation of VBR and CBR bandwidth parameters. A mechanism is provided for the dynamic allocation of subframe capacities, assignment of ABR slots based on desired queueing rules, assignment of VBR slots based on ATM traffic shaper parameters and assignment of CBR slots based on bandwidth requirements.

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

Abstract: This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2/spl pi/ radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface. >

Solid electrolytic capacitor and method for manufacturing the same

Abstract: A solid electrolytic capacitor using a conductive polymeric compound as a solid electrolyte is disclosed, wherein a powder is dispersed in the conductive polymer to provide unevenness on the surface of the solid electrolyte, thereby increasing the surface area, whereby a mechanical adhesion between the solid electrolyte and a cathode conductor layer is increased. The conductive polymer comprises a first conductive polymer layer which contacts a dielectric layer at an anode body side, and a second conductive polymer layer which contacts the cathode conductor layer side, and the powder is dispersed in the second conductive polymer layer. By this constitution, tan δ and an equivalent series resistance (ESR) of the solid electrolytic capacitor are decreased.