NEC

About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.

QoS control middleware in integrated network, QoS control method, and the program for the same

Abstract: An integrated QoS control system is provided that transmits, in real time, the stream data between a bandwidth-guaranteed network and a bandwidth-not-guaranteed network. The QoS manager 102 records the remaining bandwidth of the bandwidth-guaranteed network 2 captured by the remaining bandwidth table capturer 103 and the remaining bandwidth of the bandwidth-not-guaranteed network 1 calculated with traffic information notified by the network status monitor 107 on the use bandwidth registration table 104 (for comprehensively managing the bandwidth of an integrated network). The Qos manager 102 converts a QoS parameter received via the QoS request receiver 106 into a traffic parameter and controllably adapts the value of the traffic parameter to a service quality required by the application 109.

Planarized interlayer insulating film formed of stacked BPSG film and ozone-teos NSG film in semiconductor device and method for forming the same

Abstract: A semiconductor device formed at a substrate surface region is coated with a non-doped CVD silicon oxide film, and an interlayer insulating film composed of a BPSG film, a first ozone-TEOS NSG film and a second ozone-TEOS NSG film is formed on the silicon oxide film. The BPSG film has a thickness of not less than 50 nm but not greater than 200 nm, and is heat-treated at a temperature of not lower than 700° C. but not higher than 800° C. In addition, the first and second zone-TEOS NSG films are also heat-treated at a temperature of not lower than 700° C. but not higher than 800° C.

Code compression for low power embedded system design

Abstract: We propose instruction code compression as an efficient method for reducing power on an embedded system. Our approach is the first one to measure and optimize the power consumption of a complete SOC (System--On--a--Chip) comprising a CPU, instruction cache, data cache, main memory, data buses and address bus through code compression. We compare the pre-cache architecture (decompressor between main memory and cache) to a novel post-cache architecture (decompressor between cache and CPU). Our simulations and synthesis results show that our methodology results in large energy savings between 22% and 82% compared to the same system without code compression. Furthermore, we demonstrate that power savings come with reduced chip area and the same or even improved performance.

0.18-/spl mu/m CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation

Abstract: A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-/spl mu/m CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors.

Slurry for chemical-mechanical polishing

Abstract: By using a polishing slurry which comprises, at least, a polishing grain, an oxidizing agent and a higher-mono-primary amine, it is possible to suppress dishing and erosion liable to be produced in chemical mechanical polishing (CMP) for a copper-based metal film when forming a buried interconnection of a copper-based metal on a barrier metal film of a tantalum-based metal.