NEC

About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.

Card verification system and card verification method

Abstract: A card verification system in which a card identification code is registered. A read unit reads the card identification code from the card. A verification apparatus verifies the card only when an existing place of the read unit belongs to an area corresponding to the card identification code. The card is a card used for settlement, and is used when the card identification code is read by the read unit. The use place of the card is coincident with the existing place of the read unit. By adding the use place of the card to a verification condition of the card, unjust use of the card can be prevented.

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

Abstract: A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13

Floorplanning using a tree representation

Abstract: We present an ordered tree (O tree) structure to represent nonslicing floorplans. The O tree uses only n(2+[lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n!2/sup 2n-2//n/sup l.5/). This is very concise compared to a sequence pair representation that has O((n!)/sup 2/) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n/sup 2/(n/4e)/sup n/). The complexity of O tree is even smaller than a binary tree structure for slicing floorplan that has O(n!2/sup 5n-3//n/sup 1.5/) combinations. Given an O tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over previous central processing unit (CPU) intensive cluster refinement method.

Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals

Abstract: A synchronous dynamic random access memory device latches external command signals for defining the internal sequence, and an input circuit produces an internal control signal from a system clock signal and a clock enable signal for latching the external command signals, wherein the input circuit maintains the internal control signal in an active level for a predetermined time period regardless of the duty ratio of the external clock signal so that a malfunction hardly takes place.

Semiconductor memory device having peripheral circuit and interface circuit fabricated on bulk region out of silicon-on-insulator region for memory cells

Abstract: A semiconductor dynamic random access memory device has a memory cell array (31) fabricated on a silicon-on-insulator region (30a) and peripheral and interface circuits (32/33) fabricated on a bulk region (30b); even if the circuit components of the peripheral circuit (32) are increased together with the memory cells, the bulk region (30b) effectively radiates the heat generated by the peripheral and interface circuits (32/33), thereby preventing the memory cells from a temperature rise.