Motorola

About: Motorola is a company organization based out in Schaumburg, Illinois, United States. It is known for research contribution in the topics: Signal & Communications system. The organization has 27298 authors who have published 38274 publications receiving 968710 citations. The organization is also known as: Motorola, Inc. & Galvin Manufacturing Corporation.

High performance overmolded electronic package

Abstract: A package for containing high performance electronic components, such as high speed integrated circuits (ICs). The package bears a substrate of multiple layers having a cavity therein. Leads may be placed within holes in the substrate and soldered or otherwise electrically connected to conductive patterns or layers in the substrate. A thermally conductive insert is attached to one side of the substate. The insert has a pedestal which protrudes through the cavity in the substrate. An electronic component, such as an IC may then be mounted on the pedestal and electrically connected to a conductive metal pattern on one of the layers of the substrate. This assembly may then be coated with a dielectric material to form the package body, leaving the distal ends of the leads and the back side of the insert exposed. Since the IC chip or other component is directly mounted on the insert, waste heat generated by the chip may be directly channeled outside the package through the insert which effectively forms one wall of the package. The exposed leads may be formed into the desired configuration, including shapes suitable for surface mount technology. The use of a multiple layer substate permits the inclusion of ground and power planes for high performance circuits, such as emitter coupled logic (ECL) gate arrays, within the package itself.

Method for communicating variable length messages between a primary station and remote stations of a data communications system.

Abstract: A data communications system (Fig. 1) in which variable length messages (Figs. 3, 4 and 5) are communicated between a general communications controller (GCC 104) and a plurality of portable and mobile radios (130, 132, 134, 136, 138). The variable length messages (Fig. 3) include a bit synchronization field (204), a message synchronization field (205) and a plurality of channel data blocks (203) for efficiently and reliably handling long strings of data or text. Each channel data block (Fig. 5) includes an information field (503), a parity field (505) for error-connecting the information field and a channel state field (507) indicating whether or not the radio channel is busy or free. The GCC (104) is coupled to a cellular arrangement of channel communications modules (CCM's 106, 108, 110, 112), which each include a radio transmitter (114, 120, 124) and/or radio receiver (116, 118, 122, 126, 128). The mobile and portable radios (130, 132, 134, 136, 138) communicate with the GCC (104) by way of the CCM's (106, 108, 110, 112).

Packet delivery system

Abstract: A packet switching system (100) having a packet switch (140) employs an acknowledgment scheme in order assure the delivery of all fragments (310) comprising a fragmented data packet (300) to improve overall system throughput during the handling of packets (310) that require reassembly. When packet fragments (310) are lost, corrupted or otherwise unintelligible to a receiving device (92, 94), the acknowledgment scheme permits retransmission of the missing data. In addition, a second acknowledgment signal is scheduled by system processing resources (110) in order to verify the successful delivery of all retransmitted data.

Statistical timing analysis using bounds and selective enumeration

Abstract: The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds and selective enumeration to refine these bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. If the computed bounds are not sufficiently close to each other, we propose the use of a heuristic to iteratively improve the bounds using selective enumeration of the sample space with additional run time. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error, which could be further reduced using selective enumeration with modest additional run time.

Output circuit for interfacing integrated circuits having different power supply potentials

Abstract: An output driver circuit has a circuitry portion (70) which is used to generate a Drive-Hi control signal in response to an Output Enable, an optional Precondition signal, and a Data Input signal. A circuit portion (75) ensures that the Drive-Hi control signal is maintained at a voltage which is substantially equal to Vdd when the Output Enable is deactivated. Circuit portion (80) selectively controls the Data Output by driving Vdd onto the Data Output in response to the Drive-Hi control signal being activated. A circuit portion (100) functions to selectively drive the Data Output to a logic zero (ground potential) when a Drive-Lo signal is asserted. Circuit portions (90 and 95) generate the Drive-Lo signal in response to the Output Enable, the optional Precondition signal, and the Data Input signal. In general, the output driver circuit allows an integrated circuit powered at a first voltage to interface to another integrated circuit which is powered at a higher second voltage without loss of performance, without excessive leakage currents, without crossover current, and without increasing gate oxide stresses.