Germanium Based Field-Effect Transistors: Challenges and Opportunities
Patrick S. Goley,Mantu K. Hudait +1 more
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TLDR
This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.Abstract:
The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.read more
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High-K materials and metal gates for CMOS applications
John Robertson,Robert M. Wallace +1 more
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Synthesis and Characterization of Hexagonal Boron Nitride as a Gate Dielectric
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Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions
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TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
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Ultra-doped n-type germanium thin films for sensing in the mid-infrared
Slawomir Prucnal,Fang Liu,Matthias Voelskow,Lasse Vines,Lars Rebohle,Denny Lang,Yonder Berencén,Stefan Andric,Roman Boettger,Manfred Helm,Manfred Helm,Shengqiang Zhou,Wolfgang Skorupa +12 more
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
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Bending induced electrical response variations in ultra-thin flexible chips and device modeling
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References
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Defect reduction of selective Ge epitaxy in trenches on Si(001) substrates using aspect ratio trapping
TL;DR: In this article, a defect-free germanium was demonstrated in SiO2 trenches on silicon via aspect ratio trapping, whereby defects arising from lattice mismatch are trapped by laterally confining sidewalls.
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Ge-Photodetectors for Si-Based Optoelectronic Integration
Jian Wang,Sungjoo Lee +1 more
TL;DR: The recent progress in the development and integration of Ge-photodetectors on Si-based photonics will be comprehensively reviewed, along with remaining technological issues to be overcome and future research trends.
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A Significant Shift of Schottky Barrier Heights at Strongly Pinned Metal/Germanium Interface by Inserting an Ultra-Thin Insulating Film
TL;DR: In this paper, a gradual change of Schottky barrier heights with increasing insulating film thickness has been found, which supports that the origin of Fermi level pinning at the metal/germanium junction is caused by the metal-induced gap states.
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A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs
TL;DR: In this article, a novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, i.e., SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs).
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Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides
TL;DR: A quantum-mechanical model was developed to help understand finite inversion layer width, threshold voltage shift, and polysilicon gate depletion effects and it allows a consistent determination of the physical oxide thickness based on an excellent agreement between the measured and modeled C-V curves.