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Understanding Delta-Sigma Data Converters

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TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Journal ArticleDOI

A high-resolution low-power and multi-bit incremental converter with smart-DEM

TL;DR: A second-order 3-bit incremental converter, which employs a novel Smart-DEM algorithm to compensate for the mismatch among unity elements of the multi-level digital-to-analog converter is described in this article.

Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

TL;DR: The technologies available to perform in the likely measurement and control applications that arise within accelerators are discussed, including much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types.
Journal ArticleDOI

Delta-Sigma Digital Current Sensor Based On GMR

TL;DR: In this design, a GMR sensor which is configured as a Wheatstone bridge of four spin-valve sensing elements is integrated with CMOS signal processing circuit together, and the output signal is converted to digital domain by an on-chip 10-bit delta-sigma ADC.
Proceedings ArticleDOI

Passive slew rate enhancement technique for Switched-Capacitor Circuits

TL;DR: A passive charge compensation technique is proposed for switched capacitor circuits which increases the slew rate of its amplifiers by adding a small amount of circuitry with low power consumption to achieve higher linearity.
Journal ArticleDOI

An improved single-loop sigma-delta modulator for GSM applications

TL;DR: An improved 4th-order 1-bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.
References
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Journal ArticleDOI

A higher order topology for interpolative modulators for oversampling A/D converters

TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI

Decimation for Sigma Delta Modulation

TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI

An analysis of nonlinear behavior in delta - sigma modulators

TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI

The Structure of Quantization Noise from Sigma-Delta Modulation

TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI

A fourth-order bandpass sigma-delta modulator

TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.