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Understanding Delta-Sigma Data Converters

TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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A unified framework for the analysis and design of networked control systems

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A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 µW, 78 pA rms , 400 V/s FSCV Sensing

TL;DR: A system-on-chip (SoC) fabricated in AMS 0.35 μm 2P/4M CMOS for high-fidelity neurochemical pattern generation in vivo that uniquely integrates electrical stimulation with embedded timing management for generation of neurochemical patterns and 400 V/s fast-scan cyclic voltammetry (FSCV) sensing for subsequent assessment of fidelity in the generated profiles.
Journal ArticleDOI

Adaptive CMOS analog circuits for 4G mobile terminals-Review and state-of-the-art survey

TL;DR: A comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems is addressed.
Journal ArticleDOI

A Continuous-Time Zoom ADC for Low-Power Audio Applications

TL;DR: A high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta–sigma modulator (CTDSM) for audio applications that achieves a Schreier figure of merit (FoM) of 183.6 dB.
Journal ArticleDOI

Delta-Sigma FDC Based Fractional-N PLLs

TL;DR: A linearized model of the PLL, design criteria to avoid spurious tones in the ΔΣFDC quantization noise, and a design methodology for choosing the loop parameters in terms of standard PLL target specifications are presented.
References
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Journal ArticleDOI

A higher order topology for interpolative modulators for oversampling A/D converters

TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI

Decimation for Sigma Delta Modulation

TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI

An analysis of nonlinear behavior in delta - sigma modulators

TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI

The Structure of Quantization Noise from Sigma-Delta Modulation

TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI

A fourth-order bandpass sigma-delta modulator

TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.