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Understanding Delta-Sigma Data Converters

TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Proceedings ArticleDOI

Optimization of modulator and circuits for low power continuous-time Delta-Sigma ADC

TL;DR: A new optimization method for achieving a minimum current consumption in a continuous-time Delta-Sigma analog-to-digital converter (ADC) with active-RC integrators and with a folded-cascode operational transconductance amplifier is presented.
Journal ArticleDOI

Design Constraints for Image-Reject Frequency-Translating $\Delta\Sigma$ Modulators

TL;DR: The derived constraints offer a valuable reference for the design of image-reject frequency-translating ΔΣ ADCs that are designed with image- reject (quadrature) mixing and that are implemented using continuous- or discrete-time lowpass or complex-bandpass inner-loop Δ΢ modulators.
Journal ArticleDOI

Modeling and Analysis of Drift-Cancellation Techniques for Time-Based Integrated Resistive Sensor Interfaces

TL;DR: In this article, the drift error analysis of the integrated resistive sensor interfaces and its improvement using the drift-cancellation techniques are presented. But, the authors do not consider the non-ideal effects resulting from mismatch and nonlinearity, which still create a residual drift error of the order of 0.5% of the full scale.
Proceedings ArticleDOI

A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 /spl mu/V DC offset

TL;DR: In this paper, a low power 22-bit incremental ADC, including an on-chip digital filter and a low noise/low drift oscillator, was realized in a 0.6-/spl mu/m CMOS process.

Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces

TL;DR: Implantable neural interfaces are microelectronic systems, which have the potential to enable a wide range of applications, such as diagnosis and treatment of neurological disorders.
References
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Journal ArticleDOI

A higher order topology for interpolative modulators for oversampling A/D converters

TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI

Decimation for Sigma Delta Modulation

TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI

An analysis of nonlinear behavior in delta - sigma modulators

TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI

The Structure of Quantization Noise from Sigma-Delta Modulation

TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI

A fourth-order bandpass sigma-delta modulator

TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.