Open AccessBook
Understanding Delta-Sigma Data Converters
TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.Abstract:
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.read more
Citations
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Journal ArticleDOI
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation
TL;DR: The presented modulator suppresses the VCOQ voltage-to-frequency nonlinearity through dual path cancellation to achieve high linearity and exhibits strong immunity to the first stage quantization error leakage to the output due to gain mismatches between the two stages.
Journal ArticleDOI
A Reconfigurable DT $\Delta \Sigma $ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers
TL;DR: This paper presents an optimized switched-capacitor loop filter implementation that maximizes the achievable sampling rate by deploying an early regeneration of the quantizer and describes the system level planning, the architectural design, and the VLSI implementation of a reconfigurable discrete-time ΔΣ ADC for a multi-standard 2G/3G/4G wireless receiver.
Journal ArticleDOI
Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures
Anton Blad,Oscar Gustafsson +1 more
TL;DR: The focus is on the efficient pipelined reduction of the partial products, which is done using a bit-level optimization algorithm for the tree design, and may be used in other applications where high-speed reduction of partial products is required.
Journal ArticleDOI
Continuous-Time $\Delta \Sigma $ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC
TL;DR: The switched-capacitor return-to-zero (SCRZ) DAC is introduced, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC and is borne out by measurement results from a modulator that achieves a DR/SNR/SNDR of 87.3 dB.
Proceedings ArticleDOI
A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply
TL;DR: This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements, which achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods.
References
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Journal ArticleDOI
A higher order topology for interpolative modulators for oversampling A/D converters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI
Decimation for Sigma Delta Modulation
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI
An analysis of nonlinear behavior in delta - sigma modulators
Sasan H. Ardalan,J.J. Paulos +1 more
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI
The Structure of Quantization Noise from Sigma-Delta Modulation
James C. Candy,O. Benjamin +1 more
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI
A fourth-order bandpass sigma-delta modulator
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.