Open AccessBook
Understanding Delta-Sigma Data Converters
TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.Abstract:
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.read more
Citations
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Proceedings ArticleDOI
Dual quantization continuous time ΣΔ modulators with spectrally shaped feedback
Hossein Pakniat,Mohammad Yavari +1 more
TL;DR: A new technique is proposed to eliminate the nonlinear error of a multibit digital-to-analog converter (DAC) used in a sigma-delta modulator where the solidity ofMultibit DAC against the clock jitter is reserved.
Book ChapterDOI
Stability Analysis of Continuous Time Sigma Delta Modulators
Kyung Kang,Peter Stubberud +1 more
TL;DR: An analytical root locus method is used to determine the stability criteria for CT ΣΔMs that include exponential functions in their signal transfer functions and noise transfer functions.
Journal ArticleDOI
Low voltage Delta-Sigma Modulator with full range and unidirectional output
Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology
TL;DR: This work focuses on novel receiver architectures that address the design challenges associated with LTE-Advance from two perspectives: a receiver that is capable of wide-frequency range of operation to cover all the LTE bands and a single highly linear RF frontend to support non-contiguous-in-band CA.
Journal ArticleDOI
Binary Weighted DAC with 2-ξ Resistor Ratio
TL;DR: A new digital analog converter (DAC) design, based on the binary weighted resistor network, is presented, which ensures high conversion accuracy using low precision resistors with ±1%, ±2%, ±5%, ±10% and ±20% resistor tolerance.
References
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Journal ArticleDOI
A higher order topology for interpolative modulators for oversampling A/D converters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI
Decimation for Sigma Delta Modulation
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI
An analysis of nonlinear behavior in delta - sigma modulators
Sasan H. Ardalan,J.J. Paulos +1 more
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI
The Structure of Quantization Noise from Sigma-Delta Modulation
James C. Candy,O. Benjamin +1 more
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI
A fourth-order bandpass sigma-delta modulator
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.