Open AccessBook
Understanding Delta-Sigma Data Converters
TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.Abstract:
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.read more
Citations
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Journal ArticleDOI
A 16 bit 20 kHz bandwidth discrete-time ΣΔ modulator with VCO-based quantizer
TL;DR: In this paper the design of a 3rd-order 16 bit 20 kHz-bandwidth discrete-time ΣΔ modulator with voltage-controlled oscillator (VCO)-based quantizer is presented, motivated by the trends towards die size and power consumption reduction together with performance robustness.
Journal ArticleDOI
The Design of CIFF Structure Three-Order Switched-Capacitor Sigma-Delta Modulator
Jun Han,Wei Dong Wang +1 more
TL;DR: In this paper, a single-loop three-order switched-capacitor sigma-delta modulator (SDM) with a standard 0.18um CMOS technology is presented.
Proceedings ArticleDOI
A 16bit ΔΣ modulator design with suppressing odd-order harmonic distortions
TL;DR: In this paper, a folded-cascode op-amp with source-degeneration was designed to suppress nonlinearity in a ΔΣ modulator, and the PSD analysis of the modulator output showed that the third and fifth harmonics are both less then −100dB with the effective resolution up to 15 bits.
Book ChapterDOI
A Digitally-Assisted Electrothermal Frequency-Locked Loop in Standard CMOS
TL;DR: This chapter proposes a digitally-assisted FLL (DAFLL) architecture that mitigates the integration difficulties of previous FLLs and does not require off-chip analog components.
Method to Validate High Speed Bit-Stream Generation in Post Silicon
TL;DR: In this paper , a more reliable and controlled method of validating the HSPDM bit-stream generation is presented, which is used in next generation of automotive micro-controller.
References
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Journal ArticleDOI
A higher order topology for interpolative modulators for oversampling A/D converters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI
Decimation for Sigma Delta Modulation
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI
An analysis of nonlinear behavior in delta - sigma modulators
Sasan H. Ardalan,J.J. Paulos +1 more
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI
The Structure of Quantization Noise from Sigma-Delta Modulation
James C. Candy,O. Benjamin +1 more
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI
A fourth-order bandpass sigma-delta modulator
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.