Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
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TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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An electrostatic analytical modeling of high-k stacked gate-all-around heterojunction tunnel FETs considering the depletion regions
C. Usha,Palanichamy Vimala +1 more
TL;DR: In this paper, the analytical modelling of high-k stacked Gate-All-Around Heterojunction Tunnel Field Effect Transistor (GAA-HJTFET) considering the depletion regions is presented.
Journal ArticleDOI
Comparison of TFETs and CMOS Using Optimal Design Points for Power–Speed Tradeoffs
Juan Núñez,Maria J. Avedillo +1 more
TL;DR: In this article, the authors evaluated the performance of different fan-in logic gates using a set of widely accepted power speed metrics, including logic depth, switching activity, and minimum supply voltage.
Journal ArticleDOI
Impact-Ionization and Tunneling FET Characteristics of Dual-Functional Devices With Partially Covered Intrinsic Regions
TL;DR: In this article, dual-functional devices based on gated p-i-n diodes are proposed, which function not only as n-channel tunneling field effect transistors (n-TFETs) but also as p-channel impact-ionization FETs (p-IFETs), depending on the bias conditions.
Journal ArticleDOI
Valley interference and spin exchange at the atomic scale in silicon
Benoit Voisin,Juanita Bocquel,Archana Tankasala,Muhammad Usman,Joe Salfi,Rajib Rahman,Rajib Rahman,Michelle Y. Simmons,Lloyd C. L. Hollenberg,Sven Rogge +9 more
TL;DR: In this paper, the role of envelope anisotropy, valley interference and dopant placement on the Heisenberg spin exchange interaction was investigated in the context of scanning tunneling microscopy.
Journal ArticleDOI
All-Graphene Planar Double-Quantum-Dot Resonant Tunneling Diodes
TL;DR: In this article, a planar double-quantum-dot RTD with a single graphene nanoribbon is proposed, and its transport properties are investigated using quantum simulations based on nonequilibrium Green's function formalism and the extended Huckel method.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.