Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal ArticleDOI
Ge p-channel tunneling FETs with steep phosphorus profile source junctions
TL;DR: In this paper, the solid phase diffusion processes of three n-type dopants, i.e., phosphorus (P), arsenic (As), and antimony (Sb), from spin-on-glass (SOG) into Ge are compared.
Proceedings ArticleDOI
SiGe on SOI nanowire array TFETs with homo- and heterostructure tunnel junctions
S. Richter,Sebastian Blaeser,Lars Knoll,Stefan Trellenkamp,A. Schafer,J.M. Hartmann,Qing-Tai Zhao,S. Mantl +7 more
TL;DR: In this paper, a SiGe-Si heter-structured TFET with a vertical tunneling junction consisting of an in situ doped SiGe source and a Si channel is demonstrated, which shows switching behavior over a drain current range of up to 8 orders of magnitude with a minimum slope of 90 mV/dec.
Journal ArticleDOI
Impact of trap charge and temperature on DC and Analog/RF performances of hetero structure overlapped PNPN tunnel FET
TL;DR: In this paper, a dual dielectric constant spacer source/drain, overlapped double gate tunnel FET with a source pocket was investigated using two-dimensional Technology Computer-Aided Design (TCAD) device simulator.
Journal ArticleDOI
Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective
TL;DR: In this article, the authors investigate a detailed comparative analysis of leakage currents present with or without short channel effects in MOS devices including junctionless transistor and compare them with the ON-state current.
Journal ArticleDOI
Dual-function surfactant strategy for two-dimensional organic semiconductor crystals towards high-performance organic field-effect transistors
TL;DR: In this article, a dual-function surfactant strategy is used to control the growth of large-area few-molecular-layer 2D organic semiconductor crystals.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.