Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal Article
Negative Capacitance in a Ferroelectric Capacitor
Asif Islam Khan,Korok Chatterjee,Brian Wang,Steven Drapcho,Long You,Claudy Serrao,Saidur Rahman Bakaul,Ramamoorthy Ramesh,Sayeef Salahuddin +8 more
TL;DR: In this paper, negative capacitance in a thin epitaxial ferroelectric film was observed to decrease with time, in exactly the opposite direction to which voltage for a regular capacitor should change.
Journal ArticleDOI
Steep-slope hysteresis-free negative capacitance MoS 2 transistors
Mengwei Si,Chun-Jung Su,Chunsheng Jiang,Chunsheng Jiang,Nathan J. Conrad,Hong Zhou,Kerry Maize,Gang Qiu,Chien-Ting Wu,Ali Shakouri,Muhammad A. Alam,Peide D. Ye +11 more
TL;DR: In this article, a two-dimensional steep-slope MOSFET with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack is presented.
Journal ArticleDOI
MoS2 Field-Effect Transistor with Sub-10 nm Channel Length
Amirhasan Nourbakhsh,Ahmad Zubair,Redwan N. Sajjad,K G Amir Tavakkoli,Wei Chen,Shiang Fang,Xi Ling,Jing Kong,Mildred S. Dresselhaus,Efthimios Kaxiras,Karl K. Berggren,Dimitri A. Antoniadis,Tomas Palacios +12 more
TL;DR: The experimental results presented in this work, combined with device transport modeling, reveal the remarkable potential of 2D MoS2 for future sub-10 nm technology nodes.
Journal ArticleDOI
Promises and prospects of two-dimensional transistors
TL;DR: In this article, the authors review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking two-dimensional transistors.
Proceedings ArticleDOI
Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse
TL;DR: Four key approaches are discussed - the four horsemen - that have emerged as top contenders for thriving in the dark silicon age and each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.