Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
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TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal ArticleDOI
Tunnel Field-Effect Transistors in 2D Transition Metal Dichalcogenide Materials
Hesameddin Ilatikhameneh,Yaohua Tan,Bozidar Novakovic,Gerhard Klimeck,Rajib Rahman,Joerg Appenzeller +5 more
TL;DR: In this paper, the performance of tunnel field effect transistors (TFETs) based on two-dimensional Transition Metal Dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations.
Proceedings ArticleDOI
Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction
TL;DR: In this article, the authors proposed tunneling field effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors using InAs NW/Si heterjunction TFET with surrounding-gate architecture and high-k dielectrics.
Journal ArticleDOI
Vertical nanowire array-based field effect transistors for ultimate scaling
Guilhem Larrieu,Xiang-Lei Han +1 more
TL;DR: The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography, important in the large-scale manufacture of low-power transistors and memory devices.
Journal ArticleDOI
A Landscape of the New Dark Silicon Design Regime
TL;DR: The author proposes a set of evolutionary dark silicon design principles and examines how one of the "darkest" computing architectures of all, the human brain, trades off energy and area in ways that provide potential insights into more revolutionary directions for computer architecture.
Journal ArticleDOI
Dually active silicon nanowire transistors and circuits with equal electron and hole transport.
TL;DR: Novel multifunctional nanocircuits built from nanowire transistors that uniquely feature equal electron and hole conduction are presented, showing the mandatory requirement to yield energy efficient circuits with a single type of transistor is shown for the first time.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.