Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
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TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal ArticleDOI
High Luminescence Efficiency in MoS2 Grown by Chemical Vapor Deposition
Matin Amani,Matin Amani,Robert A. Burke,Xiang Ji,Peida Zhao,Peida Zhao,Der Hsien Lien,Der Hsien Lien,Peyman Taheri,Geun Ho Ahn,Geun Ho Ahn,Daisuke Kirya,Daisuke Kirya,Joel W. Ager,Eli Yablonovitch,Eli Yablonovitch,Jing Kong,Madan Dubey,Ali Javey,Ali Javey +19 more
TL;DR: It is shown that the PL QY of CVD-grown monolayers can be improved from ∼0.1% in the as-grown case to ∼30% after treatment, with enhancement factors ranging from 100 to 1500× depending on the initial monolayer quality.
Journal ArticleDOI
Small footprint transistor architecture for photoswitching logic and in situ memory.
Chunsen Liu,Huawei Chen,Xiang Hou,Heng Zhang,Han Jun,Yu-Gang Jiang,Xiaoyang Zeng,David Wei Zhang,Peng Zhou +8 more
TL;DR: A transistor based on a two-dimensional material that can realize photoswitching logic (OR, AND) computing in a single cell and can change the logic behaviour is reported.
Journal ArticleDOI
Band engineering in transition metal dichalcogenides: Stacked versus lateral heterostructures
Yuzheng Guo,John Robertson +1 more
TL;DR: In this article, the authors calculate a large difference in the band alignments for transition metal dichalcogenide (TMD) heterojunctions when arranged in the stacked layer or lateral (in-plane) geometries, using direct supercell calculations.
Journal ArticleDOI
Modulation of Quantum Tunneling via a Vertical Two-Dimensional Black Phosphorus and Molybdenum Disulfide p-n Junction.
Xiaochi Liu,Deshun Qu,Hua-Min Li,Inyong Moon,Faisal Ahmed,Changsik Kim,Myeongjin Lee,Yongsuk Choi,Jeong Ho Cho,James Hone,Won Jong Yoo +10 more
TL;DR: This work helps to understand the fundamentals of tunneling in 2D semiconductor heterostructures and shows great potential in future applications in integrated low-power circuits.
Journal ArticleDOI
2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure
Sanjay Kumar,Ekta Goel,Kunal Singh,Balraj Singh,Prince Kumar Singh,Kamalaksha Baral,Satyabrata Jit +6 more
TL;DR: In this paper, a physics-based 2D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs with SiO2/HfO2 stacked gate-oxide structure has been developed.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.