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Journal ArticleDOI

Tunnel field-effect transistors as energy-efficient electronic switches

Adrian M. Ionescu, +1 more
- 17 Nov 2011 - 
- Vol. 479, Iss: 7373, pp 329-337
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TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

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Citations
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Carbon Nanotubes: Present and Future Commercial Applications

TL;DR: Although not yet providing compelling mechanical strength or electrical or thermal conductivities for many applications, CNT yarns and sheets already have promising performance for applications including supercapacitors, actuators, and lightweight electromagnetic shields.
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Electronics based on two-dimensional materials

TL;DR: A review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches and the performance limits and advantages, when exploited for both digital and analog applications.
Journal ArticleDOI

A subthermionic tunnel field-effect transistor with an atomically thin channel.

TL;DR: This paper demonstrates band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on and is the only planar architecture tunnel-fET to achieve subthermionic subthreshold swing over four decades of drain current, and is also the only tunnel- FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts.
Journal ArticleDOI

A III–V nanowire channel on silicon for high-performance vertical transistors

TL;DR: Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability.
Journal ArticleDOI

Ultrasensitive and Broadband MoS2 Photodetector Driven by Ferroelectrics

TL;DR: A few-layer MoS2 photodetector driven by poly(vinylidene fluoride-trifluoroethylene) ferroelectrics is achieved, tuned by the ultrahigh electrostatic field from the ferroelectric polarization.
References
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Journal ArticleDOI

Control of InAs Nanowire Growth Directions on Si

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Journal ArticleDOI

Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design

TL;DR: In this article, three different carbon nanotube (CN) field effect transistor (CNFET) designs are compared by simulation and experiment, and the authors explore the possibility of using CNs as gate-controlled tunneling devices.
Journal ArticleDOI

Device and Architecture Outlook for Beyond CMOS Switches

TL;DR: A number of unique switches have been proposed as replacements for CMOS, many of which do not even use electron charge as the state variable and pass tokens in the spin, excitonic, photonic, magnetic, quantum, or even heat domains.
Proceedings ArticleDOI

Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance

TL;DR: In this article, the Drift Tunnel FET (DTFET) was proposed to solve the TFET bipolar parasitic conduction by a novel TFET architecture, with improved OFF state control, and demonstrated functional TFET and CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow.
Proceedings Article

Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

TL;DR: In this article, the length scaling of the double gate tunnel field effect transistor (DG tunnel FET) is studied. And the authors demonstrate that while some improvements are observed, the length scale does not dramatically affect switch figures of merit such as subthreshold slope, Ion and I off, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET.
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