Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal ArticleDOI
Analysis of Graphene Tunnel Field-Effect Transistors for Analog/RF Applications
Brajesh Rawat,Roy Paily +1 more
TL;DR: In this paper, the electronic transport in zero bandgap graphene TFET (T-GFET) is studied through the selfconsistent solution of Schrodinger equation within ballistic nonequilibrium Green's function formalism, and 2-D Poisson's equation.
Journal ArticleDOI
A Comparative Study on Scaling Capabilities of Si and SiGe Nanoscale Double Gate Tunneling FETs
TL;DR: In this article, the authors investigated the performance of SiGe nanoscale double gate TFET device including low doped drain region and obtained the superior immunity of the proposed design against traps induced degradation in comparison to the conventional TFET structure.
Journal ArticleDOI
Impact of Strain on Tunneling Current and Threshold Voltage in III–V Nanowire TFETs
TL;DR: In this paper, a simulation study on the effects of different strain configurations on n-type III-V-based nanowire tunnel-FETs is presented, with the aim to determine optimal strain conditions to enhance device performance.
Journal ArticleDOI
Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application
Yukinori Morita,Koichi Fukuda,Yongxun Liu,Takahiro Mori,Wataru Mizubayashi,Shin Ichi O'uchi,Hiroshi Fuketa,Shintaro Otsuka,Shinji Migita,Meishoku Masahara,Kazuhiko Endo,Hiroyuki Ota,Takashi Matsukawa +12 more
TL;DR: In this article, Si tunnel FinFETs are used to achieve very low short-circuit current and clear voltage input-output characteristics in a CMOS inverter with Si-tuned fin channels.
Proceedings ArticleDOI
Dual workfunction hetero gate dielectric tunnel field-effect transistor performance analysis
TL;DR: In this article, a study of DC and analog/RF response of dual work function hetero gate dielectric source pocket tunnel field effect transistor (DW HGD SP TFET) is presented, where source pocket is used to enhance the tunneling of charge carrier results in increment in ON-state current.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.