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Journal ArticleDOI

Tunnel field-effect transistors as energy-efficient electronic switches

Adrian M. Ionescu, +1 more
- 17 Nov 2011 - 
- Vol. 479, Iss: 7373, pp 329-337
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TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

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Citations
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Journal ArticleDOI

Simultaneous synthesis and integration of two-dimensional electronic components

TL;DR: In this paper, the phase-patterned growth of atomic layers is used to construct 2D molybdenum ditelluride (MoTe2) as the active material, which can be used to create high performance field effect transistors (FETs) and arrays of logic devices.
Journal ArticleDOI

Imperfect two-dimensional topological insulator field-effect transistors

TL;DR: Two-dimensional topological insulator field-effect transistors that switch based on the modulation of scattering are proposed that can be made enabling high-performance and low-power electronic circuits using imperfect two-dimensionalTopological insulators.
Journal ArticleDOI

InAs/Si Hetero-Junction Nanotube Tunnel Transistors

TL;DR: Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement.
Journal ArticleDOI

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

TL;DR: In this paper, a study of band gap, gate material work function and gate dielectric engineering for enhancement of DC and analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability is presented.
Journal ArticleDOI

Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current

TL;DR: In this paper, a dual-metal-gate (DMG) TFET was proposed to achieve an inverse subthreshold slope (SS) significantly over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain-current decade or more.
References
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Proceedings Article

Physics of semiconductor devices

S. M. Sze
Journal ArticleDOI

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI

A theory of the electrical breakdown of solid dielectrics

TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.
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