Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
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TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal ArticleDOI
Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.
Jinseong Heo,Kyung-Eun Byun,Jaeho Lee,Hyun-Jong Chung,Sanghun Jeon,Seongjun Park,Sungwoo Hwang +6 more
TL;DR: This work demonstrates wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass and designs a triangular energy barrier between the graphene and metal.
Journal ArticleDOI
An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs
TL;DR: In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified, and the transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively.
Journal ArticleDOI
Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications
Manas Ranjan Tripathy,Ashish Kumar Singh,A Samad,Sweta Chander,Kamalaksha Baral,Prince Kumar Singh,Satyabrata Jit +6 more
TL;DR: In this article, the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket was investigated for the first time to enhance the carrier tunneling through the source-channel (Si) heterojunction.
Tunnel Field-Effect Transistors Based on InP-GaAs Heterostructure
TL;DR: Low-temperature measurements suggest a mechanism of trap-assisted tunneling, possibly explained by a narrow band gap segment of InGaAsP, which is fabricated from InP-GaAs heterostructure nanowires with an n-i-p doping profile.
Journal ArticleDOI
Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade
Elvedin Memisevic,Markus Hellenbrand,Erik Lind,Axel R. Persson,Saurabh Sant,Andreas Schenk,Johannes Svensson,Reine Wallenberg,Lars-Erik Wernersson +8 more
TL;DR: The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact onThe performance.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
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Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.