Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal ArticleDOI
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.
Ali Saeidi,Teodor Rosca,Elvedin Memisevic,Igor Stolichnov,Matteo Cavalieri,Lars-Erik Wernersson,Adrian M. Ionescu +6 more
TL;DR: State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.
Journal ArticleDOI
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits
Francesco Settino,Marco Lanuzza,Sebastiano Strangio,Felice Crupi,Pierpaolo Palestri,David Esseni,Luca Selmi +6 more
TL;DR: In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node.
Journal ArticleDOI
Design of GeSn-Based Heterojunction-Enhanced N-Channel Tunneling FET With Improved Subthreshold Swing and ON-State Current
Mingshan Liu,Yan Liu,Hongjuan Wang,Qingfang Zhang,Chunfu Zhang,Shengdong Hu,Yue Hao,Genquan Han +7 more
TL;DR: In this paper, a heterojunction-enhanced n-channel tunneling FET (HE-NTFET) employing a Ge1−x Sn x /Ge1− y Sn y ( $x>y$ ) heterjunction located in the channel region with a distance of $L_{\rm T-H}$ from the source channel tunneling junction was investigated.
Journal ArticleDOI
Transition from Tunneling Leakage Current to Molecular Tunneling in Single-Molecule Junctions
Junyang Liu,Xiaotao Zhao,Jueting Zheng,Xiaoyan Huang,Yongxiang Tang,Fei Wang,Ruihao Li,Jiuchan Pi,Cancan Huang,Lin Wang,Yang Yang,Jia Shi,Bing-Wei Mao,Zhong-Qun Tian,Martin R. Bryce,Wenjing Hong +15 more
TL;DR: In this paper, a series of oligo(aryleneethynylene) (OAE) molecules were employed to investigate the transition from tunneling leakage current to molecular tunneling in the single-molecule devices using a mechanically controllable break-junction technique, and the transition distances of the OAE molecular junctions were determined.
Journal ArticleDOI
Sub-10 nm two-dimensional transistors: Theory and experiment
Ruge Quhe,Lin Xu,Shiqi Liu,Chen Yang,Yangyang Wang,Hong Li,Jie Yang,Qiuhui Li,Bowen Shi,Ying Li,Yuanyuan Pan,Xiaotian Sun,Jingzhen Li,Mouyi Weng,Han Zhang,Ying Guo,Linqiang Xu,Hao Tang,Jichao Dong,Jinbo Yang,Zhiyong Zhang,Ming Lei,Feng Pan,Jing Lu +23 more
TL;DR: In this paper, the authors introduce the recent experimental and ab initio quantum transport simulation progress in the 2D FETs with a gate length less than 10nm and outline the challenges and outlook on the future development directions in the sub-10-nm 2D tunneling FET.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.