Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
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TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal ArticleDOI
Ultra‐Steep‐Slope High‐Gain MoS2 Transistors with Atomic Threshold‐Switching Gate
Jun Lin,Xiaozhang Chen,Xinpei Duan,Zhiming Yu,Wencheng Niu,Mingliang Zhang,Chang Liu,Guoli Li,Yuan Liu,Xingqiang Liu,Peng Zhou,Lei Liao +11 more
TL;DR: With the ultra-steep SS, the RG-FETs can be readily employed to construct logic inverter with an ultra-high gain ≈2000, indicating exciting potential for future low-power electronics and monolithic integration.
Journal ArticleDOI
Ultra‐Steep Slope Impact Ionization Transistors Based on Graphene/InAs Heterostructures
Proceedings ArticleDOI
Comparison between vertical silicon NW-TFET and NW-MOSFETfrom analog point of view
Paula Ghedini Der Agopian,Joao Antonio Martino,Anne Vandooren,Rita Rooyackers,Eddy Simoen,Aaron Thean,C. Claeys +6 more
TL;DR: In this article, a comparison of the analog performance between vertical silicon Nanowires Tunnel Field Effect Transistors (NW-TFETs) and nanowires MOSFETs was performed mainly focusing on the basic analog characteristics at room and high temperatures for the first time.
Journal ArticleDOI
Vertical Cladding Layer-Based Doping-Less Tunneling Field Effect Transistor: A Novel Low-Power High-Performance Device
TL;DR: In this article , a novel vertical doping-less tunnel field effect transistor (TFET) was introduced, where instead of using metal to induce charge plasma in the source region, cladding layer was utilized to engineer the energy bands in this region.
Journal ArticleDOI
InAs/Si Hetero-Junction Channel to Enhance the Performance of DG-TFET with Graphene Nanoribbon: an Analytical Model
TL;DR: In this article, a double-gate dual-metal tunnel field effect transistor (DG-TFET) with graphene nano-ribbon is presented, which improves the performance by incorporating group III-V material in source.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.