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Journal ArticleDOI

Tunnel field-effect transistors as energy-efficient electronic switches

Adrian M. Ionescu, +1 more
- 17 Nov 2011 - 
- Vol. 479, Iss: 7373, pp 329-337
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TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

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Citations
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Journal ArticleDOI

Dirac Electrons at the Source: Breaking the 60-mV/Decade Switching Limit

TL;DR: In this article, the authors show that the linear density of states (DOS) of Dirac electrons at the source concomitant with an efficient gate control brings the SS limit down to 37 mV/decade, and further down to very small values by suppressing the thermal tail contribution with a small bandgap in the injected DOS.
Journal ArticleDOI

A review of selected topics in physics based modeling for tunnel field-effect transistors

TL;DR: A hierarchy of numerical models exist for tunnel-FETs covering a wide range of predictive capabilities and computational complexities as mentioned in this paper, with a possible guidance to the wide and rapidly developing literature in this exciting research field.
Journal ArticleDOI

Spatial metrology of dopants in silicon with exact lattice site precision.

TL;DR: The demonstrated ability to determine the locations of P and As dopants to 5 nm depths will provide critical information for the design and optimization of nanoscale devices for classical and quantum computing applications.
Journal ArticleDOI

Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si

TL;DR: In this paper, the authors demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb tunneling field effect transistors integrated on Si substrates.
Journal ArticleDOI

Digital and analog TFET circuits: Design and benchmark

TL;DR: This work investigates by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs) and highlights how differences in the I-V characteristics of FinFets and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.
References
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Proceedings Article

Physics of semiconductor devices

S. M. Sze
Journal ArticleDOI

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI

A theory of the electrical breakdown of solid dielectrics

TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.
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