Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TLDR
Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.Abstract:
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.read more
Citations
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Journal ArticleDOI
Leakage current reduction in junctionless tunnel FET using a lightly doped source
TL;DR: In this paper, a technique of using a lightly doped source region, below the p-gate, was proposed to increase the barrier and prevent any leakage in junctionless tunnel field effect transistor (JLTFET).
Journal ArticleDOI
Improving the Scalability of SOI-Based Tunnel FETs Using Ground Plane in Buried Oxide
Shelly Garg,Sneh Saurabh +1 more
TL;DR: In this article, a ground plane is added to the buried oxide of a silicon-on-insulator (SOI) TFET, which depletes the drain and increases the effective source-to-drain distance.
Journal ArticleDOI
Current Status of Reliability in Extended and Beyond CMOS Devices
TL;DR: In this article, the authors present reliability concerns for a set of extended and beyond CMOS devices and show that defects in different parts of these devices require detailed study to ensure their usability in electronics industry.
Journal ArticleDOI
Realizing Logic Functions Using Single Double-Gate Tunnel FETs: A Simulation Study
TL;DR: It is demonstrated that two-input CMOS-type AND, OR, NAND, and NOR logic gates can be implemented using two DGTFETs that are designed to exhibit complimentary logic functions.
Journal ArticleDOI
Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform
Sunny Anand,Rakesh Kumar Sarin +1 more
TL;DR: In this article, a doping-less tunnel FET is proposed and investigated for the first time, in which the charge plasma technique is used to form source/drain region on an intrinsic InAs body by selecting proper work function of metal electrode.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
A theory of the electrical breakdown of solid dielectrics
TL;DR: In this paper, two distinct mechanisms have been suggested for the sudden increase of the number of electrons in an unfilled band, which occurs when the field strength passes a critical value, analogous to the electrical breakdown of gases.