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Institution

Sony Broadcast & Professional Research Laboratories

CompanyTaipei, Taiwan
About: Sony Broadcast & Professional Research Laboratories is a company organization based out in Taipei, Taiwan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 38708 authors who have published 63864 publications receiving 865637 citations.


Papers
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Patent
04 Jun 2009
TL;DR: In this paper, a method of matching a pose of a synthesised representation of a human or animal body to a captured image of that body is provided, which can be used to generate a graphical model of the body when disposed on a plane, such as a synthesized model of a football player on a field of play.
Abstract: A method of matching a pose of a synthesised representation of a human or animal body to a captured image of that human or animal body is provided, which can be used to generate a graphical model of the body when disposed on a plane, such as a synthesised model of a football player on a field of play. The method includes receiving the captured image data, determining from the captured image data a plurality of limb position estimates, each position estimate corresponding to an amount by which limbs of the body are separated with respect to each other and deriving from the plurality of limb positions an estimated gait phase of the body. The estimated gait phase is then applied to a basis gait model in order to provide an estimated pose of the body, the basis gait model comprising data which defines a displacement of the limbs or parts thereof with respect to a gait cycle period. The estimated pose is then matched to that of the synthesised representation of the body.

146 citations

Proceedings Article
26 Mar 2007
TL;DR: CLEFIA as mentioned in this paper is a 128-bit blockcipher supporting key lengths of 128, 192 and 256 bits, which is compatible with AES and achieves a good performance profile both in hardware and software.
Abstract: We propose a new 128-bit blockcipher CLEFIA supporting key lengths of 128, 192 and 256 bits, which is compatible with AES. CLEFIA achieves enough immunity against known attacks and flexibility for efficient implementation in both hardware and software by adopting several novel and state-of-the-art design techniques. CLEFIA achieves a good performance profile both in hardware and software. In hardware using a 0.09 µm CMOS ASIC library, about 1.60 Gbps with less than 6 Kgates, and in software, about 13 cycles/byte, 1.48 Gbps on 2.4 GHz AMD Athlon 64 is achieved. CLEFIA is a highly efficient blockcipher, especially in hardware.

146 citations

Patent
28 Sep 1994
TL;DR: In this paper, the look-up table contains either predictive coefficients which are used as weights for pixels of a signal in one hierarchical level to produce a signal at a higher hierarchical level, or representative values which are combined with a dynamic range and redundant component in a set of pixels of an input signal in a one-level hierarchical encoding system to produce an output signal at the higher level.
Abstract: In a hierarchical encoding apparatus, predictors each including a look-up table are used to form predicted signals for respective hierarchical levels. The difference between the predicted signal and the original signal forms the differential signal for the higher hierarchical levels. The look-up table contains either predictive coefficients which are used as weights for pixels of a signal in one hierarchical level to produce a signal at a higher hierarchical level, or representative values which are combined with a dynamic range and redundant component in a set of pixels of a signal in one hierarchical level to produce a signal at a higher hierarchical level. The values in the look-up table are obtained from representative images.

146 citations

Patent
23 Apr 1999
TL;DR: In this article, the number of light sources and number of divided light beams are optimized, so that a light beam with sufficiently reduced speckle contrast can be used as illuminating light, and when the light path length difference from one point on the spatial modulator to an image corresponding thereto has a standard deviation σZ, the number M and the number N are set so that the relation expressed by the following expression A is satisfied.
Abstract: The number of light sources and the number of divided light beams are optimized, so that a light beam with sufficiently reduced speckle contrast can be used as illuminating light. In an optical system for forming an image through a spatial modulator, laser light having a spectrum width of wave number and emitted from N (N is an integer not less than 1) light sources is guided to a fiber bundle so that the light is divided into M light beams (M is an integer not less than 2), a light path length difference of not less than a coherent distance is given to the respective light beams, and then, light axes are again aligned with each other to illuminate the spatial modulator, and when the light path length difference from one point on the spatial modulator to an image corresponding thereto has a standard deviation σZ, the number M and the number N are set so that a relation expressed by the following expression A is satisfied: ( numerical   expression   49 )   NM · 1 + ( 2 · W · σ z ) 2 4 ≧ 1 Expression   A

146 citations

Patent
23 Sep 2009
TL;DR: In this paper, a plurality of addition means and image processing means are configured to perform second and subsequent addition processing, and generate an image of the second resolution as a processing result by performing the addition processing for a predetermined number of times.
Abstract: An image processing apparatus includes a plurality of addition means and an image processing means. The addition means performs addition processing of adding pixels of a differential image at a second resolution representing a difference between an inputted image at a first resolution and an image at the second resolution higher than the first resolution as pixels of an inputted image at the second resolution. The image processing means is configured to perform second and subsequent addition processing, and generate an image of the second resolution as a processing result by performing the addition processing for a predetermined number of times. The addition processing is performed with inputs of an image at the first resolution and an image at the second resolution obtained by an immediately preceding addition processing, which are different from each other.

146 citations


Authors

Showing all 38711 results

NameH-indexPapersCitations
Hui Li1352982105903
Susumu Kitagawa12580969594
Shree K. Nayar11338445139
Takashi Kobayashi10360651385
Bo Huang9772840135
Muhammad Imran94305351728
Xiaodong Xu94112250817
Mitsuo Kawato8642235640
Takashi Yamamoto84140135169
Atsuo Yamada7844423989
Katsushi Ikeuchi7863620622
Yoshihiro Iwasa7745427146
Satoshi Miyazaki7634120483
Hiroshi Yamazaki7495327216
Alexei Gruverman6930118610
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20223
2021294
2020902
20191,297
20181,111
20171,078