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Journal ArticleDOI

Academic and industry research progress in germanium nanodevices

Ravi Pillarisetty
- 17 Nov 2011 - 
- Vol. 479, Iss: 7373, pp 324-328
TLDR
Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract
Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.

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Citations
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Ge1-xSnx materials: Challenges and applications

TL;DR: In this article, the use of Ge1-xSnx for future (electrical) device applications and its fabrication with a special attention on recent achievements from imec was discussed, where compressive uniaxial and/or bi-axial strain implementation seems essential to substantially increase carriers velocity and to outperform current Si- and Si1-yGeybased devices, which is confirmed by theoretical calculations of the carrier mobility and device current.
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Ultimate nano-electronics

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Proceedings ArticleDOI

First experimental demonstration of Ge 3D FinFET CMOS circuits

TL;DR: In this article, the first experimental demonstration of Ge 3D CMOS circuits, based on the recessed fin structure, is reported. And the Ge FinFETs show superior gate electrostatic control over planar devices and sub-threshold slope (SS) as low as 93 and 73 mV/dec, respectively.
References
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Proceedings ArticleDOI

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Journal ArticleDOI

Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing

TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Journal ArticleDOI

High-k/Ge MOSFETs for future nanoelectronics

TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
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