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Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Proceedings ArticleDOI
Novel 140°C hybrid thin film solar cell/transistor technology with 9.6% conversion efficiency and 1.1 cm 2 /V-s electron mobility for low-temperature substrates
Chang-Hong Shen,Jia-Min Shieh,Hao-Chung Kuo,Jung Y. Huang,Wen-Hsien Huang,Chih-Wei Hsu,Yu-Hsin Lin,Hung-Yu Chiu,Huang-Yan Jhan,Bau-Tong Dai,Ching-Ting Lee,Ci-Ling Pan,Chenming Hu,Fu-Liang Yang +13 more
TL;DR: In this paper, a low temperature silicon thin film deposition technology using high density plasma for high performance and low cost solar cells with embedded transistor modules was reported. But the performance of this technology was limited to process temperature at 140°C and 60°C.
Engineering BSIM for the Nano-Technology Era and Beyond
M Chan,Chenming Hu +1 more
TL;DR: In this article, the authors present the current status of the forth generation BSIM model and issues of modeling CMOS based devices with nanometer dimensions, and propose methods to design next generation extendible device models with advanced computer programming techniques.
Journal ArticleDOI
Computer analysis on the collection of alpha-generated charge for reflecting and absorbing surface conditions around the collector
TL;DR: In this paper, the authors present an analysis of the collection of alpha-particle generated charge by collectors surrounded by either uniform reflecting or uniform absorbing surfaces, assuming that the charge transport is by diffusion.
Patent
Semiconductor structure having a strained region and a method of fabricating same
TL;DR: In this article, the top layer of a highly strained selective epitaxial top layer is formed in the uppermost series layer by forming a trench with rounded corners so that a dielectric material filling the trench conforms to the round corners.
Proceedings ArticleDOI
Scaling of CMOS FinFETs towards 10 nm
Hao-Yu Chen,Chien-Chao Huang,Cheng-Chuan Huang,Chang-Yun Chang,Yee-Chia Yeo,Fu-Liang Yang,Chenming Hu +6 more
TL;DR: CMOS FinFETs with 35 nm gate length L/sub g/ and performance parameters exceeding that of ITRS projections are fabricated and device simulations are performed to explore the scalability and optimization of FinFets to 10 nmGate length.