There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

New technologies and alternate transistor structures are being developed to extend the CMOS scaling. Device models need to be developed and improved in parallel with the technology advancements to enable an efficient and quick adoption of the new technologies. Some of the recent advances in BSIM4 and BSIM Multi-gate models towards meeting this goal are presented in this paper. Improvements to the BSIM4 model include holistic stress-induced mobility enhancement model and a high-k dynamic behavior model. Preliminary results of the modeling of multi-gate architectures are also presented.

https://briefs.techconnect.org/wp-content/volumes/Nanotech2006v3/pdf/1074.pdf

BSIM4 and BSIM Multi-Gate Progress

Oxide lifetime extrapolation using log(tBD) or better log(QBD) against 1/ Eox plot is more accurate and has a theoretical basis. Highly accelerated oxide test completed in seconds appears to be feasible. The acceleration factor is also a function of the severity of the oxide defect. Extrapolation of defect-related break-down lifetime can be performed assuming an effective oxide thinning for defects.

Accelerated Testing of Silicon Dioxide Wearout

This paper presents an approach to model the characteristics of undoped Double-Gate MOSFETs without relying on the charge-sheet approximation. Due to the extremely thin silicon film used, the inversion charge thickness becomes comparable to the silicon film thickness and cannot be ignored. Together with volume inversion and quantum effect, the carriers are distributed along the vertical direction perpendicular to the direction of current flow. Therefore, a 2D modeling approach considering vertical current distribution and lateral carrier transport is required. To simplify the 2-D problem, the quasi-Fermi potential has been taken as a reference to develop a quasi 2-D DG MOSFET model.

/pdf/quasi-2d-compact-modeling-for-double-gate-mosfet-5aaq2uwowp.pdf

Quasi-2D Compact Modeling for Double-Gate MOSFET

A method is disclosed for forming a semiconductor device using strained silicon. After forming a first substrate material with a first natural lattice constant on a device substrate and a second substrate material with a second natural lattice constant on the first substrate material, a channel, source and drain regions of a field effective transistor are further defined using the first and second substrate materials. After implanting one or more impurity materials to the source and drain regions, and the transistor goes through an annealing process using a high speed heat source other than a Tungsten-Halogen lamp.

Thermal anneal process for strained-Si devices

We demonstrate the integration of sputterdeposited ultra-thin HfO2 gate dielectric into a sub-100 nm gate length CMOS process using poly-Si as the gate material. Good device characteristics have been observed down to 70 nm physical gate length, and an equivalent gate oxide thickness (EOT) of 11A has been achieved. Both p-FETs and n-FETs with HfO2 gate dielectric show ~104 times lower gate leakage than Si02 with comparable EOT. Data and model suggest that the gate leakage of Hf02 will be lOO times lower than that of Si02 down to 5A EOT.

Chenming Hu

Papers

BSIM4 and BSIM Multi-Gate Progress

Accelerated Testing of Silicon Dioxide Wearout

Quasi-2D Compact Modeling for Double-Gate MOSFET

Thermal anneal process for strained-Si devices

Deep-submicron CMOS process integration of HfO/sub 2/ gate dielectric with poly-si gate