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Chenming Hu

Researcher at University of California, Berkeley

Publications -  1300
Citations -  60963

Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Papers
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Journal ArticleDOI

Substrate resistance calculation for latchup modeling

K.W. Terrill, +1 more
- 01 Sep 1984 - 
TL;DR: In this paper, a method to estimate the substrate potential induced by a triggering current in CMOS input and output circuits and the effect of using guard rings to prevent latchup was presented.
Proceedings ArticleDOI

Corner spacer design for performance optimization of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap

Vita Pi-Ho Hu, +4 more
TL;DR: In this paper, a corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize source/drain resistance and capacitance, and hence improve delay.
Proceedings ArticleDOI

Some issues of power MOSFETs

Min-hwa Chi, +1 more
TL;DR: In this paper, the second-breakdown of power MOSFETs is shown to be triggered by the turn-on of the parasitic bipolar transistor, and the I-V characteristics of power mOSFets operating in reverse mode (such as when used as a synchronous rectifier).
Journal ArticleDOI

Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET

Yu-Hung Liao, +8 more
- 20 Jan 2021 - 
TL;DR: In this paper, the authors used a Landau-Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, showed that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement.
Journal ArticleDOI

Mechanisms for Microstructure Evolution in Electroplated Copper Thin Films

James Mckell Edwin Harper, +6 more
- 01 Jan 1999 - 
TL;DR: In this article, the authors present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature, including an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness and compressive stress.