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Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Journal ArticleDOI
Resonant-cavity separate absorption, charge and multiplication avalanche photodiodes with high-speed and high gain-bandwidth product
H. Nie,K.A. Anselm,C. Lenox,P. Yuan,Chenming Hu,Geoffrey S. Kinsey,Ben G. Streetman,Joe C. Campbell +7 more
TL;DR: In this article, a resonant-cavity separate-absorption-and-multiplication (SAM) APD with an additional charge layer that provides better control of the electric field profile is described.
Proceedings ArticleDOI
Compact models of negative-capacitance FinFETs: Lumped and distributed charge models
Juan P. Duarte,Sourabh Khandelwal,Asif Islam Khan,Angada B. Sachid,Yen-Kai Lin,Huan-Lin Chang,Sayeef Salahuddin,Chenming Hu +7 more
TL;DR: In this article, the authors propose a lumped and distributed charge model for negative capacitance FinFETs, where the ferroelectric layer will impact the local channel charge and this distributed effect has important implications on device characteristics.
Journal ArticleDOI
Correlation Between Breakdown and Process‐Induced Positive Charge Trapping in Thin Thermal SiO2
S.E. Holland,Chenming Hu +1 more
Journal ArticleDOI
Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf 0.8 Zr 0.2 O 2 , High Endurance and Breakdown Recovery
Korok Chatterjee,Sangwan Kim,Golnaz Karbasian,Ava J. Tan,Ajay K. Yadav,Asif Islam Khan,Chenming Hu,Sayeef Salahuddin +7 more
TL;DR: In this article, a nonvolatile single transistor ferroelectric gate memory device with ultra-thin Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process is presented.
Journal ArticleDOI
SOI (Silicon-on-insulator) for high speed ultra large scale integration
TL;DR: In this article, the authors proposed a realistic target for silicon-on-insulator (SOI) delay and power reduction in comparison to bulk technology are 40% and 30%, independent of scaling.