There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

A novel normalized mutual integral difference (NMID) method is presented in this letter to extract the threshold voltage of MOSFETs. The basic principle of this method is to utilize the exponential-linear characteristics of MOSFETs current so as to obtain the normalized mutual integral difference extreme spectral characteristics. The proposed method is sensitive to channel length variation while being insensitive to parasitic resistance. The extracted results on the threshold voltage show a good consistency and have been compared with those obtained by the second-derivative technique. A good correlation between both methods has also been found.

Normalized mutual integral difference method to extract threshold voltage of MOSFETs

Ultra-thin tunnel oxide can conduct very high current through oxide via direct tunneling; charge-to-breakdown increases dramatically due to less oxide damage. These facts point to a possibility of using ultra-thin tunnel oxide in the floating-gate device structure for dynamic-memory applications. We chose MONOS structure in this study due to its immunity to defect-induced leakage and back-tunneling. The memory device exhibits fast WRITE/ERASE speed, high endurance, long data retention and non-destructive READ. Further improvements are expected through process optimization.

High endurance ultra-thin tunnel oxide for dynamic memory application

The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher I/sub dsat/ and larger I/sub sub/ TO maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V/sub dd/. For the same hot-carrier lifetime, we show that ring oscillators with asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power.

0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology

In this paper, a methodology for generating worst-case SPICE files is presented. This methodology is based upon the identification and evaluation of circuit building blocks within a design. Correlations between these block are determined for a specific circuit variable. The results show there is a high degree of correlation between NAND, NOR, inverter logic gates and NAND gates implemented in Complementary Pass Transistor Logic (CPL) with regards to speed and power dissipation. A method of resolving multiple SPICE files is also presented which produces a realistic prediction of circuit performance.

Realistic worst-case SPICE file extraction using BSIM3

A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

Chenming Hu

Papers

Normalized mutual integral difference method to extract threshold voltage of MOSFETs

High endurance ultra-thin tunnel oxide for dynamic memory application

0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology

Realistic worst-case SPICE file extraction using BSIM3

Relaxed silicon germanium substrate with low defect density