Chenming Hu

TL;DR: In this paper, random telegraph signal (RTS) measurements have been used to study individual hot-carrier-induced traps in nMOSFETs, and the trap location (3-10 A from interface), time constant ( approximately 10 ms), and energy are found to be quite different from those of prestress (process-induced) traps.

TL;DR: In this paper, an antifuse structure according to the first aspect of the present invention is programmed by snap-back breakdown and includes a semiconductor substrate of a first conductivity type, an insulating layer over the surface of the semiconductor substrategies, a conductive gate disposed over the insulating layers, spacer elements disposed at the outer edges of the conductive gates, spaced-apart first and second lightly doped regions of a second conductivities type disposed in the semiconductors, the third and fourth more heavily doped region of the second conduct

TL;DR: The dependence of 30-nm-gate MOSFET performance on body bias is experimentally evaluated for devices with various channel-doping profiles to provide guidance for channel engineering in a forward body-biasing scheme.

TL;DR: In this paper, the integration of dual damascene copper with low-k dielectric at the 0.13 /spl mu/m technology node is described, and the integration is achieved while maintaining reliability standards.

TL;DR: In this paper, the authors presented ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain.