Chenming Hu

TL;DR: In this paper, an SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over this layer.

TL;DR: In this paper, the authors used hole trapping at weak sites with local, above-average current density or large hole trap density to predict a linear relationship between in t BD and 1/F rather than E. This model provides a framework for predicting oxide reliability as a function of area and stress condition.

TL;DR: A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate as mentioned in this paper, where active devices such as transistors and diodes can be formed in the semiconductor layer.

TL;DR: In this paper, the authors discuss the recent enhancements made in the BSIM6 bulk MOSFET model and validate symmetry of the model by performing Gummel Symmetry Test (GST) in DC and symmetry test for capacitances in AC.

TL;DR: In this paper, the Ni/AlGaN interface states are proposed to be responsible for strain-induced gate barrier variations, which are important for device performances and sensor applications, and the dependence of nickel gate barrier height on external strain, which strongly affects HEMTs' threshold voltage and 2DEG concentration.