C
Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Journal ArticleDOI
Modified resistive switching behavior of ZrO2 memory films based on the interface layer formed by using Ti top electrode
TL;DR: In this paper, the influence of Ti top electrode material on the resistive switching properties of ZrO2-based memory film using Pt as bottom electrode was investigated and the experimental results imply that switching the device into high conducting state is a field driven process while switching back into low conducting state was a current driven process.
Proceedings ArticleDOI
A capacitorless double-gate DRAM cell design for high density applications
C. Kuo,Tsu-Jae King,Chenming Hu +2 more
TL;DR: In this article, a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design is investigated and the soft error problems are discussed. But careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.
Journal ArticleDOI
Electromigration and stress-induced voiding in fine Al and Al-alloy thin-filmed lines
TL;DR: Physical phenomena underlying failure due to electromigration and stress-induced voiding in fine Al and Al-alloy thin-film conducting lines are examined in the context of accelerated testing methods and structures.
Journal ArticleDOI
Stress-induced oxide leakage
R. Rofan,Chenming Hu +1 more
TL;DR: In this paper, a correlation between the leakage current and the charge-pumping current was evident in a series of voltage stress, annealing, and restress tests, suggesting that the leakage may be a result of the oxide-trap assisted tunneling.
Patent
Doping of semiconductor fin devices
TL;DR: In this paper, the dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surfaces.