There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

We suggest a method to estimate the effects of substrate resistances on the latchup holding voltage of CMOS integrated circuits. The estimated holding voltages are shown to be in reasonable agreement with the experimental data inspite of two bold approximations. Using this method, we analyze the effect of several variables relating to the epitaxial substrate and/or the well-isolation trench on the latchup holding voltage. It is shown that there may exist a certain optimum epitaxial layer thickness that leads to a maximum latchup holding voltage and that even a shallow trench is remarkably effective in raising the holding voltage. Physical explanations are offered for the effects of the epitaxial layer and trench on the holding voltage. Examples are presented to illustrate the general effects of several design variables and to aid the design and interpretation of process experiments.

Effects of substrate resistance on CMOS latchup holding voltages

A new technique determined the J‐E characteristics of silicon dioxide grown from polycrystalline silicon with greatly improved sensitivity. More importantly, the current density was measured over a 10‐decade range without the problem of current drift or uncertainty about the field at the cathode surface due to charge trapping in the oxide. The apparent barrier height decreased with increasing electric field as if the barrier lowering was due to field enhancement at surface asperities of about 500 A in size. The technique is applicable to other dielectrics where charge trapping presents difficulties to J‐E measurements.

Current‐field characteristics of oxides grown from polycrystalline silicon

A novel and simple method of growing oxides of multiple thicknesses using oxygen implant in sub-5 nm gate oxide technologies is presented. Results show that multiple thicknesses on the same wafer can be achieved with good interface and bulk properties of the oxide. Oxygen implant produces oxides with better Q/sub BD/ characteristics than the nitrogen-implanted oxides.

Sub-5 nm multiple-thickness gate oxide technology using oxygen implantation

A spacer lithography process technology using a sacrificial layer and a CVD (Chemical Vapor Deposition) spacer layer has been developed, and is demonstrated to achieve sub-40 nm structures with conventional dry etching. The minimum-sized features are defined not by photolithography but by the CVD film thickness. Therefore the spacer lithography technology yields CD (Critical Dimension) variations of minimum-sized features which are much smaller than achieved by optical or e-beam lithography. It also provides a doubling of device density for a given lithography pitch. This spacer lithography technology is used to pattern Si-fin structures for double-gate MOSFETs (FinFETs), and CMOS FinFET results are reported.

Spacer FinFET: nano-scale CMOS technology for the terabit era

A structure of multiple-gate transistor and method for manufacturing the same is described. The structure includes a vertical semiconductor fin, a gate dielectric layer, a gate electrode, and a source and a drain. The semiconductor fin is disposed on a substrate. The substrate includes a first insulator layer overlying an etch-stop layer. An undercut is formed in the first insulator layer beneath the semiconductor fin. The gate dielectric layer covers the semiconductor fin, and the gate electrode covers the gate dielectric layer. The source and the drain formed in the semiconductor fin are separated by the gate electrode.

Chenming Hu

Papers

Effects of substrate resistance on CMOS latchup holding voltages

Current‐field characteristics of oxides grown from polycrystalline silicon

Sub-5 nm multiple-thickness gate oxide technology using oxygen implantation

Spacer FinFET: nano-scale CMOS technology for the terabit era

Structure of multiple-gate transistor and method for manufacturing the same