Chenming Hu

TL;DR: Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported, paving the way to high-density, ultralow-voltage, and ultralowing-power applications.

TL;DR: This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects, which could simulate the layout dependence of MOS performance with good accuracy and efficiency.

TL;DR: Nano-wires as discussed by the authors can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric.

TL;DR: Ta/sub 2/O/sub 5/ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide in this article.

TL;DR: In this article, the authors examined the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator, which can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances.