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Chenming Hu

Researcher at University of California, Berkeley

Publications -  1300
Citations -  60963

Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Papers
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Journal ArticleDOI

Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support

TL;DR: In this article, a type-III broken gap band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin tunneling barrier, is demonstrated with a quasi-stationary 2-D TCAD Sentaurus device simulation.
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Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport

TL;DR: In this article, a unified compact model for carrier transport from the drift-diffusion to the ballistic regime is presented, which accounts for carrier degeneracy effects in ballistic transport and is implemented into the industry standard compact models for FinFETs, fully depleted silicon-on-insulator (FDSOI) devices and bulk MOSFET.
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Optimization of epitaxial layers for power bipolar-MOS transistor

TL;DR: In this paper, the effect of epitaxial layer design on the performance of the power bipolar-MOS transistor, also known as IGT and COMFET, was studied.
Journal Article

Reliability Challenges with Ultra-Low k Interlevel Dielectrics.

TL;DR: This paper reviews work performed in the laboratory to understand and characterize these new and temperamental materials and concludes that low mechanical strength, low elastic modulus, rapid diffusion and susceptibility to dielectric breakdown are all characteristic of the ULK dielectrics.
Proceedings ArticleDOI

Temperature and current effects on small-geometry-contact resistance

TL;DR: In this paper, the effects of temperature and current on the resistance of small geometry silicided contact structures have been characterized and modeled for the first time, and it was shown that temperature and high current induced self heating can cause contact resistance lowering which can be significant in the performance of advanced ICs.