There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Existing literature indicates that there are two major mechanisms involved in the time dependent dielectric breakdown (TDDB) of silicon dioxide, and each mechanism dominates under different stress conditions. We suggest that the thermochemical (linear E) model and the hole-induced (1/E) model can be unified in one model. Based on the unified model, a wide range of TDDB data from different sources were examined and shown to behave consistently. Temperature and stress field dependencies are treated together in the model so that the lifetime is a single-valued function of temperature and field. The criterion for screen/ramp breakdown test is also discussed with the model. Furthermore, the unified model accounts for the effect of gross defects, which limit the oxide reliability in real ICs. The model is be used to predict the 10-year lifetime breakdown field or acceptable oxide thickness for a given voltage, and results suggest that further refinements for thin oxide (<5 nm) are necessary.

A unified gate oxide reliability model

A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.

Dual work function CMOS gate technology based on metal interdiffusion

A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

Strained channel complementary field-effect transistors and methods of manufacture

This paper presents the first statistical model of Vt fluctuation (ΔVtcell) in a floating-gate flash memory due to random telegraph noise. It considers current-path percolation, which generates a large-amplitude-noise tail, caused by dopant induced surface potential non-uniformity It concludes that the impact of scaling is weaker than the widely-accepted 1/LeffWeff trend. 3-σ ΔVtcell is estimated to increase by 1.8x rather than ≫10x from 90 nm to 20 nm technology nodes.

Random telegraph noise in flash memories - model and technology scaling

Semiconductor device and method of fabricating the same. A semiconductor device in accordance with the invention includes a gate dielectric overlying a channel region. A source region and a drain region are disposed on opposing sides of the channel region, where the channel region is comprised of a first semiconductor material and the source and drain regions are comprised of a second semiconductor material. A gate electrode overlies the gate dielectric and first and second spacers are formed on sides of the gate electrode, wherein each of the spacers includes a void adjacent to the channel region.

Chenming Hu

Papers

A unified gate oxide reliability model

Dual work function CMOS gate technology based on metal interdiffusion

Strained channel complementary field-effect transistors and methods of manufacture

Random telegraph noise in flash memories - model and technology scaling

Semiconductor device and method of fabricating the same